基于FPGA与MATLAB的fir滤波器实现（Verilog）

ADDRESS_ACLR_A=NONE CLOCK_ENABLE_INPUT_A=BYPASS CLOCK_ENABLE_OUTPUT_A=BYPASS INIT_FILE=fir_parr_8.hex INTENDED_DEVICE_FAMILY="Cyclone IV E" NUMWORDS_A=4096 OPERATION_MODE=ROM OUTDATA_ACLR_A=NONE OUTDATA_REG_A=UNREGISTERED RAM_BLOCK_TYPE=M9K WIDTHAD_A=12 WIDTH_A=12 WIDTH_BYTEENA_A=1 DEVICE_FAMILY="Cyclone IV E" address_a clock0 q_a