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Order Number: 241618-034

Intel

Processor Identification and

the CPUID Instruction

Application Note 485

March 2009

2 Application Note

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,

BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,

AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING

LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY

PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving,

life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future

changes to them.

Intel processors may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained

by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel, Pentium, Pentium M, Celeron, Celeron M, Intel NetBurst, Intel Xeon, Pentium II Xeon, Pentium III Xeon, Intel SpeedStep,

OverDrive, MMX, Intel486, Intel386, IntelDX2, Core Solo, Core Duo, Core 2 Duo, Atom, Core i7 and the Intel logo are trademarks

or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

† Hyper-Threading Technology requires a computer system with an Intel® processor supporting Hyper-Threading Technology and

an HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and

software you use. See http://www.intel.com/products/ht/hyperthreading_more.htm for more information including details on

which processors support HT Technology.

* Other brands and names may be claimed as the property of others.

Application Note 3

Contents

1Introduction..............................................................................................................9

1.1 Update Support...................................................................................................9

2 Detecting the CPUID Instruction .............................................................................11

3 Output of the CPUID Instruction..............................................................................13

3.1 Standard CPUID Functions..................................................................................15

3.1.1 Vendor-ID and Largest Standard Function (Function 0)................................15

3.1.2 Feature Information (Function 1)..............................................................15

3.1.3 Cache Descriptors (Function 2) ................................................................ 25

3.1.4 Processor Serial Number (Function 3) .......................................................29

3.1.5 Deterministic Cache Parameters (Function 4)............................................. 29

3.1.6 MONITOR / MWAIT Parameters (Function 5) ..............................................31

3.1.7 Digital Thermal Sensor and Power Management Parameters (Function 6)....... 31

3.1.8 Reserved (Function 7)............................................................................. 32

3.1.9 Reserved (Function 8)............................................................................. 32

3.1.10 Direct Cache Access (DCA) Parameters (Function 9).................................... 32

3.1.11 Architectural Performance Monitor Features (Function 0Ah)..........................32

3.1.12 x2APIC Features / Processor Topology (Function 0Bh).................................33

3.1.13 Reserved (Function 0Ch).........................................................................35

3.1.14 XSAVE Features (Function 0Dh) ...............................................................35

3.2 Extended CPUID Functions .................................................................................35

3.2.1 Largest Extended Function # (Function 8000_0000h).................................. 35

3.2.2 Extended Feature Bits (Function 8000_0001h) ........................................... 36

3.2.3 Processor Name / Brand String (Function 8000_0002h, 8000_0003h,

8000_0004h)......................................................................................... 36

3.2.4 Reserved (Function 8000_0005h)............................................................. 38

3.2.5 Extended L2 Cache Features (Function 8000_0006h) .................................. 38

3.2.6 Advanced Power Management (Function 8000_0007h) ................................ 39

3.2.7 Virtual and Physical address Sizes (Function 8000_0008h)........................... 39

4 Processor Serial Number .........................................................................................41

4.1 Presence of Processor Serial Number ...................................................................41

4.2 Forming the 96-bit Processor Serial Number .........................................................42

5 Brand ID and Brand String.......................................................................................43

5.1 Brand ID..........................................................................................................43

5.2 Brand String.....................................................................................................44

6 Usage Guidelines.....................................................................................................45

7 Proper Identification Sequence ...............................................................................47

8 Denormals Are Zero................................................................................................. 49

9 Operating Frequency ...............................................................................................51

10 Program Examples ..................................................................................................53

4 Application Note

Figures

2-1 Flag Register Evolution.......................................................................................11

3-1 CPUID Instruction Outputs..................................................................................14

3-2 EDX Register After RESET...................................................................................15

3-3 Processor Signature Format on Intel386™ Processors.............................................17

3-4 Extended Feature Flag Values Reported in the EDX Register ....................................36

3-5 L2 Cache Details................................................................................................38

7-1 Flow of Processor get_cpu_type Procedure............................................................48

10-1 Flow of Processor Identification Extraction Procedure..............................................53

Tables

3-1 Processor Type (Bit Positions 13 and 12)...............................................................16

3-2 Intel386™ Processor Signatures ..........................................................................17

3-3 Intel486™ and Subsequent Processor Signatures ...................................................17

3-4 Feature Flag Values Reported in the EDX Register ..................................................21

3-5 Feature Flag Values Reported in the ECX Register ..................................................24

3-6 Descriptor Formats ............................................................................................26

3-7 Descriptor Decode Values ...................................................................................26

3-8 Intel® Core™ i7 Processor, Model 1Ah with 8-MB L3 Cache CPUID (EAX=2) ..............28

3-9 Deterministic Cache Parameters ..........................................................................29

3-10 MONITOR / MWAIT Parameters............................................................................31

3-11 Digital Sensor and Power Management Parameters ................................................31

3-12 DCA Parameters ................................................................................................32

3-13 Performance Monitor Features.............................................................................32

3-14 Core / Logical Processor Topology Overview ..........................................................33

3-15 Thread Level Processor Topology (CPUID Function 0Bh with ECX=0).........................34

3-16 Core Level Processor Topology (CPUID Function 0Bh with ECX=1)............................34

3-17 Core Level Processor Topology (CPUID Function 0Bh with ECX>=2)..........................34

3-18 Processor Extended State Enumeration.................................................................35

3-19 Largest Extended Function..................................................................................35

3-20 Extended Feature Flag Values Reported in the ECX Register.....................................36

3-21 Power Management Details .................................................................................39

3-22 Virtual and Physical Address Size Definitions .........................................................39

5-1 Brand ID (EAX=1) Return Values in EBX (Bits 7 through 9) .....................................43

5-2 Processor Brand String Feature............................................................................44

Examples

3-1 Building the Processor Brand String......................................................................37

3-2 Displaying the Processor Brand String ..................................................................38

10-1 Processor Identification Extraction Procedure.........................................................54

10-2 Processor Identification Procedure in Assembly Language........................................62

10-3 Processor Identification Procedure in the C Language..............................................83

10-4 Detecting Denormals-Are-Zero Support ................................................................92

10-5 Frequency Detection ..........................................................................................96

Application Note 5

Revision History

Revision Description Date

-001 Original release. 05/93

-002 Modified Table 3-3 Intel486™ and Pentium® Processor Signatures. 10/93

-003

Updated to accommodate new processor versions. Program examples modified for ease of

use, section added discussing BIOS recognition for OverDrive® processors and feature flag

information updated.

09/94

-004

Updated with Pentium Pro and OverDrive processors information. Modified, Table 3-2, and

Table 3-3. Inserted Table 3-5. Feature Flag Values Reported in the ECX Register. Inserted

Sections 3.4. and 3.5.

12/95

-005

Added Figure 2-1 and Figure 3-2. Added Footnotes 1 and 2. Added Assembly code example

in Section 4. Modified Tables 3, 5 and 7. Added two bullets in Section 5.0. Modified

cpuid3b.ASM and cpuid3b.C programs to determine if processor features MMX™ technology.

Modified Figure 6.0.

11/96

-006

Modified Table 3. Added reserved for future member of P6 family of processors entry.

Modified table header to reflect Pentium II processor family. Modified Table 5. Added SEP bit

definition. Added Section 3.5. Added Section 3.7 and Table 9. Corrected references of P6

family to reflect correct usage.

Modified cpuid3a.asm, cpuid3b.asm and cpuid3.c example code sections to check for SEP

feature bit and to check for, and identify, the Pentium II processor. Added additional

disclaimer related to designers and errata.

03/97

-007

Modified Table 2. Added Pentium II processor, model 5 entry. Modified existing Pentium II

processor entry to read “Pentium II processor, model 3”. Modified Table 5. Added additional

feature bits, PAT and FXSR. Modified Table 7. Added entries 44h and 45h.

Removed the note “Do not assume a value of 1 in a feature flag indicates that a given

feature is present. For future feature flags, a value of 1 may indicate that the specific feature

is not present” in section 4.0.

Modified cpuid3b.asm and cpuid3.c example code section to check for, and identify, the

Pentium II processor, model 5. Modified existing Pentium II processor code to print Pentium

II processor, model 3.

01/98

-008

Added note to identify Intel® Celeron® processor, model 5 in section 3.2. Modified Table 2.

Added Celeron processor and Pentium® OverDrive® processor with MMX™ technology

entry. Modified Table 5. Added additional feature bit, PSE-36.

Modified cpuid3b.asm and cpuid3.c example code to check for, and identify, the Celeron

processor.

04/98

-009

Added note to identify Pentium II Xeon® processor in section 3.2. Modified Table 2. Added

Pentium II Xeon processor entry.

Modified cpuid3b.asm and cpuid3.c example code to check for, and identify, the Pentium II

Xeon processor.

06/98

-010 No Changes

-011

Modified Table 2. Added Celeron processor, model 6 entry.

Modified cpuid3b.asm and cpuid3.c example code to check for, and identify, the Celeron

processor, model 6.

12/98

-012

Modified Figure 1 to add the reserved information for the Intel386 processors. Modified

Figure 2. Added the Processor serial number information returned when the CPUID

instruction is executed with EAX=3. Modified Table 1. Added the Processor serial number

parameter. Modified Table 2. Added the Pentium III processor and Pentium III Xeon

processor. Added Section 4 “Processor serial number”.

Modified cpuid3a.asm, cpuid3b.asm and cpuid3.c example code to check for and identify the

Pentium III processor and the Pentium III Xeon processor.

12/98

-013

Modified Figure 2. Added the Brand ID information returned when the CPUID instruction is

executed with EAX=1. Added section 5 “Brand ID”. Added Table 10 that shows the defined

Brand ID values.

Modified cpuid3a.asm, cpuid3b.asm and cpuid3.c example code to check for and identify the

Pentium III processor, model 8 and the Pentium III Xeon processor, model 8.

10/99

-014 Modified Table 4. Added Celeron processor, model 8. 03/00

-015

Modified Table 4. Added Pentium III Xeon processor, model A. Added the 8-way set

associative 1M, and 8-way set associative 2M cache descriptor entries.

05/00

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