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Application Note BCM538X/BCM5396
02/12/07
Broadcom Corporation
Document 538X_5396-AN103-R Page v
Section 5: Programming Interfaces ................................................................................. 30
SPI Compatible Programming Interface ...................................................................................................30
External PHY Registers .........................................................................................................................31
Clock Polarity and Phase.......................................................................................................................31
Read And Write Examples.....................................................................................................................32
Normal Mode Read ........................................................................................................................32
Fast Mode Read .............................................................................................................................34
Normal Mode Write.........................................................................................................................35
EEPROM Interface Connection..................................................................................................................37
MDC/MDIO Interface ...................................................................................................................................38
Master: External PHY Registers ............................................................................................................39
Internal SerDes Transceiver and Pseudo PHY .....................................................................................40
BCM5396 Dual MDC/MDIO...................................................................................................................41
Section 6: Power Considerations..................................................................................... 42
Supply Voltages..........................................................................................................................................42
Core and I/O Power Sequencing Requirements....................................................................................42
IR Drops.................................................................................................................................................43
Input Voltage and Noise Tolerance .......................................................................................................44
Design Considerations for Main Power Supply .......................................................................................44
Power Supply Filter Components Recommendations ............................................................................45
General Guidelines ................................................................................................................................45
Power and Ground Planes .............................................................................................................45
Decoupling Capacitors ...................................................................................................................45
Bulk Filter Capacitors .....................................................................................................................45
Specific Power Supply Decoupling Recommendations .........................................................................46
PLLAVDD, PLLAVDD2...................................................................................................................46
SAVDD ...........................................................................................................................................46
DVDD .............................................................................................................................................46
PLLDVDD .......................................................................................................................................46
OVDD/VDDO33/VDDO25 ..............................................................................................................46
OVDD2/VDDO25............................................................................................................................46
XTALVDD .......................................................................................................................................46
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