The emergence of the new advanced package technology chip scale package (CSP) in the semiconductor industry has been increasingly becoming popular. In this study, the focus
will be made on the CSP package types using wire bonding interconnect technology, which was performed to determine the degree of limitation and challenges of having a short and low looping profile as dictated by the allowable CSP package thickness. Two major considerations were studied and investigated, namely: the short and low wire looping
profile, and capillary design.