PCIe_vs_Eth_vs_RapdIO
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Backplane tutorial: RapidIO, PCIe and Ethernet
Barry Wood, Tundra
1/14/2009 12:00 PM EST
While there are many ways to connect components in embedded systems, the most prominent are the
high speed serial standards of Ethernet, PCI Express, and RapidIO. All of these standards leverage
similar Serializer/De-serializer (SerDes) technology to deliver throughput and latency performance
greater than what is possible with wide parallel bus technology. For example, RapidIO and PCI Express
leveraged the XAUI SerDes technology developed for Ethernet.
The trend towards leveraging a common SerDes technology will continue with future versions of these
specifications. The implication is that raw bandwidth is not a significant differentiator for these protocols.
Instead, the usefulness of each protocol is determined by how the bandwidth is used.
Protocol summaries
Most designers are familiar with basic Ethernet protocol characteristics. Ethernet is a 'best effort' means
of delivering packets. The software protocols built on top of the Ethernet physical layer, such as TCP/IP,
are necessary to provide reliable delivery of information, as Ethernet-based systems generally perform
flow control at the network layer, not the physical layer. Typically, the bandwidth of Ethernet-based
systems is over-provisioned by between 20 and 70%. Ethernet is best suited for high latency inter-
chassis applications or on-board/inter-board applications where bandwidth requirements are low.
PCI Express (PCIe), in contrast, is optimized for reliable delivery of packets within an on-board
interconnect where latencies are typically in the microsecond range. The PCIe protocol exchanges
Transaction Layer Packets (TLPs) such as reads and writes, and smaller quantities of link-specific
information called Data Link Layer Packets (DLLPs). DLLPs are used for link management functions,
including physical layer flow control. PCIe was designed to be backwards compatible with the legacy of
PCI and PCI-X devices, which assumed that the processor(s) sat at the top of a hierarchy of buses. This
had the advantage of leveraging PCI-related software and hardware intellectual property. As discussed
later in this article, the PCI bus legacy places significant constraints on the switched PCIe protocol.
RapidIO technology has been optimized for embedded systems, particularly those which require
multiple processing elements to cooperate. Like PCIe, the RapidIO protocol exchanges packets and
smaller quantities of link-specific information called control symbols. RapidIO has characteristics of both
PCIe and Ethernet. For example, RapidIO provides both reliable and unreliable packet delivery
mechanisms. RapidIO also has many unique capabilities which make it the optimal interconnect for on-
board, inter-board, and short distance (<100 m) inter-chassis applications.
Physical layer
At the physical/link layer, the protocols have very different capabilities when it comes to flow control and
error recovery. Ethernet flow control is primarily implemented in software at the network layer, as this is
the most effective for large networks. Ethernet's only physical layer flow control mechanism is PAUSE,
which halts transmission for a specified period of time. The limited physical layer flow control means that
Ethernet networks discard packets to deal with congestion.
In contrast, PCIe and RapidIO physical-layer flow control mechanisms ensure reliable delivery of
packets. Each packet is retained by the transmitter until it is acknowledged. If a transmission error is
detected, a link maintenance protocol ensures that corrupted packets are retransmitted.
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