电子密码锁vhdl语言源程序

LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity e_latch is
   port(clk:in std_logic;
        k0:in std_logic;
        k1:in std_logic; 
        clr:in std_logic;
        load:in std_logic;
        lt:out std_logic;
        lamp:out std_logic_vector(7 downto 0);
        lf:out std_logic;
        alm:out std_logic); 
end e_latch;

architecture Behavioral of e_latch is
signal shift,lock:std_logic_vector(7 downto 0):="00000000";

signal lam:std_logic_vector(7 downto 0);
signal la,li:std_logic;
begin
process(clk,clr)
 begin
   if clr='0' then
   la<='0';
   li<='0';
elsif clk'event and clk='1' then
   if load='0' then