xilinx u-boot

Driver Model ============ This README contains high-level information about driver model, a unified way of declaring and accessing drivers in U-Boot. The original work was done by: Marek Vasut <marex@denx.de> Pavel Herrmann <morpheus.ibis@gmail.com> Viktor Křivák <viktor.krivak@gmail.com> Tomas Hlavacek <tmshlvck@gmail.com> This has been both simplified and extended into the current implementation by: Simon Glass <sjg@chromium.org> Terminology ----------- Uclass - a group of devices which operate in the same way. A uclass provides a way of accessing individual devices within the group, but always using the same interface. For example a GPIO uclass provides operations for get/set value. An I2C uclass may have 10 I2C ports, 4 with one driver, and 6 with another. Driver - some code which talks to a peripheral and presents a higher-level interface to it. Device - an instance of a driver, tied to a particular port or peripheral. How to try it ------------- Build U-Boot sandbox and run it: make sandbox_defconfig make ./u-boot -d u-boot.dtb (type 'reset' to exit U-Boot) There is a uclass called 'demo'. This uclass handles saying hello, and reporting its status. There are two drivers in this uclass: - simple: Just prints a message for hello, doesn't implement status - shape: Prints shapes and reports number of characters printed as status The demo class is pretty simple, but not trivial. The intention is that it can be used for testing, so it will implement all driver model features and provide good code coverage of them. It does have multiple drivers, it handles parameter data and platdata (data which tells the driver how to operate on a particular platform) and it uses private driver data. To try it, see the example session below: =>demo hello 1 Hello '@' from 07981110: red 4 =>demo status 2 Status: 0 =>demo hello 2 g r@ e@@ e@@@ n@@@@ g@@@@@ =>demo status 2 Status: 21 =>demo hello 4 ^ y^^^ e^^^^^ l^^^^^^^ l^^^^^^^ o^^^^^ w^^^ =>demo status 4 Status: 36 => Running the tests ----------------- The intent with driver model is that the core portion has 100% test coverage in sandbox, and every uclass has its own test. As a move towards this, tests are provided in test/dm. To run them, try: ./test/py/test.py --bd sandbox --build -k ut_dm -v You should see something like this: (venv)$ ./test/py/test.py --bd sandbox --build -k ut_dm -v +make O=/root/u-boot/build-sandbox -s sandbox_defconfig +make O=/root/u-boot/build-sandbox -s -j8 ============================= test session starts ============================== platform linux2 -- Python 2.7.5, pytest-2.9.0, py-1.4.31, pluggy-0.3.1 -- /root/u-boot/venv/bin/python cachedir: .cache rootdir: /root/u-boot, inifile: collected 199 items test/py/tests/test_ut.py::test_ut_dm_init PASSED test/py/tests/test_ut.py::test_ut[ut_dm_adc_bind] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_adc_multi_channel_conversion] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_adc_multi_channel_shot] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_conversion] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_shot] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_adc_supply] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_adc_wrong_channel_selection] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_autobind] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_autobind_uclass_pdata_alloc] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_autobind_uclass_pdata_valid] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_autoprobe] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_bus_child_post_bind] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_bus_child_post_bind_uclass] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_bus_child_pre_probe_uclass] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_bus_children] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_bus_children_funcs] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_bus_children_iterators] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_data] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_data_uclass] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_ops] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_platdata] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_platdata_uclass] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_children] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_clk_base] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_clk_periph] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_device_get_uclass_id] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_eth] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_eth_act] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_eth_alias] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_eth_prime] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_eth_rotate] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_fdt] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_fdt_offset] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_fdt_pre_reloc] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_fdt_uclass_seq] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_gpio] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_gpio_anon] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_gpio_copy] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_gpio_leak] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_gpio_phandles] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_gpio_requestf] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_i2c_bytewise] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_i2c_find] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_i2c_offset] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_i2c_offset_len] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_i2c_probe_empty] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_i2c_read_write] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_i2c_speed] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_leak] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_led_base] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_led_gpio] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_led_label] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_lifecycle] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_mmc_base] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_net_retry] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_operations] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_ordering] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_pci_base] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_pci_busnum] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_pci_swapcase] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_platdata] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_get] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_io] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_autoset] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_autoset_list] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_get] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_current] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_enable] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_mode] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_voltage] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_pre_reloc] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_ram_base] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_regmap_base] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_regmap_syscon] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_remoteproc_base] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_remove] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_reset_base] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_reset_walk] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_rtc_base] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_rtc_dual] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_rtc_reset] PASSED test/py/tests/test_ut.py::test_ut[ut_dm_rtc_set_get] PASS