Intel指令集.pdf
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Appendix D: Instruction Set Reference
This section provides encodings and approximate cycle times for all instructions that you would nor-
mally execute in
real
mode on an Intel processor. Missing are the special instructions on the 80286 and
later processors that manipulate page tables, segment descriptors, and other instructions that only an oper-
ating system should use. The cycle times are approximate. To determine exact execution times, you will
need to run an experiment. The cycle times are given for comparison purposes only.
Key to special bits in encodings:
x: Don’t care. Can be zero or one.
s: Sign extension bit for immediate operands. If zero, immediate operand is 16 or 32 bits depend-
ing on destination operand size. If s bit is one, then the immediate operand is eight bits and the
CPU sign extends to 16 or 32 bits, as appropriate.
rrr: Same as reg field in [mod-reg-r/m] byte.
Other Notes:
[disp] This field can be zero, one, two, or four bytes long as required by the instruction.
[imm] This field is one byte long if the operand is an eight bit operand or if the
s
bit in the instruction
opcode is one. It is two or four bytes long if the
s
bit contains zero and the destination operand
is 16 or 32 bits, respectively.
[mod-reg-r/m]: Instructions that have a mod-reg-r/m byte may have a scaled index byte (sib) and a zero, one,
two, or four byte displacement. See Appendix E for details concerning the encoding of this por-
tion of the instruction.
reg,reg Many instructions allow two operands using a [mod-reg-r/m] byte. A single
direction
bit in the
opcode determines whether the instruction treats the
reg
operand as the destination or the mod-
r/m operand as the destination (e.g., mov reg,mem vs. mov mem,reg). Such instructions also
allow two register operands. It turns out there are two encodings for each such reg-reg instruc-
tion. That is, you can encode an instruction like mov ax, bx with ax encoded in the reg field and
bx encoded in the mod-r/m field, or you can encode it with bx encoded in the reg field and ax
encoded in the mod-r/m field. Such instructions always have an
x
bit in the opcode. If the
x
bit
is zero, the destination is the register specified by the mod-r/m field. If the
x
bit is one, the desti-
nation is the register specified by the reg field. Other types of instructions support multiple
encodings for similar reasons.
Table 97: 80x86 Instruction Set Reference
a
Instruction
Encoding
(bin)
b
Execution Time in Cycles
c
8088 8086 80286 80386 80486 Pentium
aaa 0011 0111883433
aad 1101 0101
0000 1010
60 60 14 19 14 10
aam 1101 0100
0000 1010
83 83 16 17 15 18
aas 0011 1111 883433
adc reg8, reg8 0001 00x0
[11-reg-r/m]
3‘32211
adc reg16, reg16 0001 00x1
[11-reg-r/m]
332211
Thi d d i h F M k 4 0 2
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