Preliminary Information
USB3.0 Board Layout Guideline
Document No ISG-NC1-200060-01
Date Published Feb.28. 2011
Printed in Japan
www.renesas.com
[MEMO]
No. ISG-NC1-200060-01
Renesas Electronics Confidential
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the
products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General
Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in
the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
The input pins of CMOS products are generally in the high-impedance state. In operation with
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register settings and
pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins
are not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
When the clock signal is generated with an external resonator (or from an external oscillator)
during a reset, ensure that the reset line is only released after full stabilization of the clock signal.
Moreover, when switching to a clock signal produced with an external resonator (or by an external
oscillator) while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm that the
change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different part numbers, implement a system-evaluation test for each of the products.
USB logo is a trademark of USB Implementers Forum, Inc.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
No. ISG-NC1-200060-01
Renesas Electronics Confidential
4
No. ISG-NC1-200060-01
Renesas Electronics Confidential
Contents
1. Introduction........................................................................................................................ 6
2. Overview on USB 3.0......................................................................................................... 7
3. USB 3.0 Board Design Guidelines................................................................................... 8
3.1. The SS trace length.......................................................................................................... 9
3.2. AC coupling capacitor on the SS signal trace pair...................................................... 10
3.3. Trace crossing................................................................................................................. 11
3.4. Adjacent trace.................................................................................................................. 12
3.5. Number of the layer......................................................................................................... 13
3.6. Ground plane ................................................................................................................... 14
3.7. Line impedance ............................................................................................................... 17
3.8. Symmetrical routing........................................................................................................20
3.9. Stub on signal traces ......................................................................................................21
3.10. Trace Bending ................................................................................................................. 22
3.11. Routing around USB receptacle .................................................................................... 23
3.12. Routing around USB LSI................................................................................................. 30
4. Example for signal routing for µPD720200/A Host controller..................................... 33
5. References ....................................................................................................................... 34
6.
Layout Q&A List .............................................................................................................. 35
7. USB3.0 Board Layout Check List .................................................................................. 37
8. Appendix .......................................................................................................................... 38
9. History .............................................................................................................................. 39
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