5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet
of
COVER PAGE 1.1A
Altera Cyclone II Starter Board
B
121Tuesday, October 03, 2006
Title
Size Document Number Rev
Date: Sheet
of
COVER PAGE 1.1A
Altera Cyclone II Starter Board
B
121Tuesday, October 03, 2006
Title
Size Document Number Rev
Date: Sheet
of
COVER PAGE 1.1A
Altera Cyclone II Starter Board
B
121Tuesday, October 03, 2006
18 ~ 19
TOP 01 ~ 03
04 ~ 04
21 ~ 21
PAGE
05 ~ 07
13 ~ 17
SCHEMATIC
Altera Cyclone II FPGA Starter Board
20 ~ 20
CONTENT
COVER PAGE , TOP
AUDIO WM8731
DISPLAY VGA , 7SEGMENT ,LED
EP2C20 EP2C20 BANK1..BANK8 , POWER , CONFIG 08 ~ 12
INPUT CLOCK , PS2 , RS232 , KEY , SWITCH , CONNECT
MEMORY SRAM , DRAM , FLASH , SD CARD
POWER POWER
BLASTER USB BLASTER
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet
of
PLACEMENT 1.1A
Altera Cyclone II Starter Board
B
221Tuesday, October 03, 2006
Title
Size Document Number Rev
Date: Sheet
of
PLACEMENT 1.1A
Altera Cyclone II Starter Board
B
221Tuesday, October 03, 2006
Title
Size Document Number Rev
Date: Sheet
of
PLACEMENT 1.1A
Altera Cyclone II Starter Board
B
221Tuesday, October 03, 2006
LINE
IN
LINE
OUT
MIC
IN
WM8731
VGA
OUTPUT
PS2
KEYBORAD
RS232
SD CARD
4BIT RGB
EP2C20
FLASHSRAMSDRAM
GPIO_1
GPIO_0
EXT CLK
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW9
HEX0
HEX1
HEX2
HEX3
M3128
EPCS4
FT245
LED10
LED11
LED12
LED13
LED14
LED15
LED16
LED17
KEY0
KEY1
KEY2
KEY3
USB
BLASTER
DC
7.5V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AUD_BCLK
AUD_DACDAT
AUD_ADCLRCK
AUD_DACLRCK
I2C_SCLK
AUD_XCK
AUD_ADCDAT
DATA0
TDO
NSTATUS
NCSO
NCE
CONF_DONE
TCK
NCONFIG
TDI
TMS
ASDO
DCLK
HEX0_D[0..6]
HEX1_D[0..6]
HEX2_D[0..6]
SW[0..9]
KEY[0..3]
UART_RXD
50MHZ
EXT_CLOCK
PS2_DAT
PS2_CLK
UART_TXD
SD_CLK
27MHZ
FLASH_OE
FLASH_RESET
I2C_SCLK
EXT_CLOCK
KEY[0..3]
UART_RXD
PS2_DAT
SD_CMD
FLASH_A[0..21]
FLASH_CE
SD_DAT3
TDO
DATA0
50MHZ
SW[0..2]
FLASH_WE
LINK_D0
LINK_D1
LINK_D2LINK_D3
27MHZ
HEX3_D[0..6]
VGA_B[0..3]
VGA_R[0..3]
VGA_G[0..3]
LED[0..17]
VGA_VSYNC
VGA_HSYNC
SW[3..6]
SW[7..9]
GPIO_B[0..71]
GPIO_B[0..35]
24MHZ
GPIO_B[36..71]
FLASH_CE
FLASH_OE
FLASH_A[0..21]
DRAM_A[0..11]
SRAM_A[0..17]
DRAM_LDQM
DRAM_UDQM
DRAM_CLK
DRAM_CKE
DRAM_BA0
DRAM_BA1
DRAM_WE
DRAM_CAS
DRAM_RAS
DRAM_CS
SRAM_WE
SRAM_CE
SRAM_OE
SRAM_UB
SRAM_LB
SD_DAT3
SD_CMD
SD_CLK
FLASH_RESET
FLASH_WE
FLASH_D[0..7]
DRAM_D[0..15]
SRAM_D[0..15]
SD_DAT
I2C_SDAT
UART_TXD
AUD_ADCLRCK
AUD_BCLK
AUD_DACDAT
AUD_DACLRCK
AUD_XCK
PS2_CLK
NCONFIG
TMS
TDI
CONF_DONE
NSTATUS
NCE
TCK
ASDO
AUD_ADCDAT
I2C_SDAT
VGA_HSYNC
VGA_VSYNC
VGA_R[0..3]
VGA_G[0..3]
VGA_B[0..3]
LED[0..17]
LINK_D3
LINK_D0
LINK_D1
NCSO
DCLK
24MHZ
SD_DAT
LINK_D2
SRAM_D[0..15]
FLASH_D[0..7]
SRAM_CE
SRAM_WE
SRAM_OE
SRAM_UB
SRAM_LB
DRAM_CS
DRAM_BA1
DRAM_CAS
DRAM_CLK
DRAM_D[0..15]
DRAM_LDQM
DRAM_UDQM
DRAM_BA0
DRAM_RAS
DRAM_CKE
DRAM_WE
SRAM_A[0..17]
DRAM_A[0..11]
HEX3_D[0..6]
HEX2_D[0..6]
HEX1_D[0..6]
HEX0_D[0..6]
Title
Size Document Number Rev
Date: Sheet
of
TOP LEVEL 1.1A
Altera Cyclone II Starter Board
B
321Tuesday, October 03, 2006
Title
Size Document Number Rev
Date: Sheet
of
TOP LEVEL 1.1A
Altera Cyclone II Starter Board
B
321Tuesday, October 03, 2006
Title
Size Document Number Rev
Date: Sheet
of
TOP LEVEL 1.1A
Altera Cyclone II Starter Board
B
321Tuesday, October 03, 2006
INPUT IN/OUT
PS2_CLK
PS2_DAT
UART_TXD UART_RXD
KEY[0..3]
50MHZ
EXT_CLOCK
27MHZ
SW[0..9]
GPIO_B[0..35]
GPIO_B[36..71]
USB BLASTER PAGE 21
DATA0
NCSO
DCLK
ASDO
TDO
TMS
TDI
NCONFIG
TCK
CONF_DONE
NCE
NSTATUS
LINK_D3
LINK_D0
LINK_D1
LINK_D2
24MHZ
MEMORY PAGE 18-19
FLASH_RESET
FLASH_WE
FLASH_A[0..21]
FLASH_CE
FLASH_OE
FLASH_D[0..7]
DRAM_A[0..11]
DRAM_LDQM
DRAM_UDQM
DRAM_CLK
DRAM_CKE
DRAM_BA0
DRAM_BA1
DRAM_D[0..15]
DRAM_WE
DRAM_CAS
DRAM_RAS
DRAM_CS
SRAM_A[0..17] SRAM_D[0..15]
SRAM_WE
SRAM_CE
SRAM_OE
SD_DAT
SD_CMD
SD_CLK
SRAM_UB
SRAM_LB
SD_DAT3
DISPLAY PAGE 5-6
HEX0_D[0..6]
HEX1_D[0..6]
HEX2_D[0..6]
HEX3_D[0..6]
VGA_B[0..3]
VGA_G[0..3]
LED[0..17]
VGA_VSYNC
VGA_HSYNC
VGA_R[0..3]
AUDIO PAGE 4
AUD_BCLK
AUD_DACDAT
AUD_ADCLRCK
AUD_DACLRCK
AUD_ADCDAT
I2C_SDATI2C_SCLK
AUD_XCK
EP2S35 EP2C20
NCONFIG
TDI
TMS
TDO
CONF_DONE
NSTATUS
TCK
NCE
ASDO
DCLK
NCSO
DATA0
FLASH_A[0..21]
FLASH_D[0..7]
SD_DAT
SD_CLK
SD_CMD
KEY[0..3]
SRAM_CE
SRAM_WE
SRAM_A[0..17]
SRAM_D[0..15]
SRAM_OE
FLASH_CE
FLASH_OE
FLASH_RESET
FLASH_WE
27MHZ
LINK_D2
SD_DAT3
LINK_D3
AUD_XCK
AUD_BCLK
AUD_DACDAT
AUD_DACLRCK
AUD_ADCLRCK
AUD_ADCDAT
I2C_SCLK
I2C_SDAT
UART_RXD
UART_TXD
PS2_CLK
PS2_DAT
HEX3_D[0..6]
HEX2_D[0..6]
HEX1_D[0..6]
HEX0_D[0..6]
SW[0..2]
DRAM_UDQM
DRAM_LDQM
DRAM_D[0..15]
DRAM_BA1
DRAM_CS
DRAM_BA0
DRAM_RAS
DRAM_CKE
DRAM_CAS
DRAM_CLK
DRAM_WE
DRAM_A[0..11]
50MHZ
EXT_CLOCK
SRAM_UB
SRAM_LB
LINK_D0
LINK_D1
VGA_B[0..3]
VGA_G[0..3]
VGA_VSYNC
VGA_HSYNC
VGA_R[0..3]
LED[0..17]
SW[3..6]
SW[7..9]
24MHZ
GPIO_B[0..71]
PWR PAGE 20
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C_SCLK
I2C_SDAT
AUD_BCLK
AUD_DACDAT
AUD_ADCLRCK
AUD_DACLRCK
AUD_ADCDAT
I2C_SDAT
I2C_SCLK
AUD_XCK
A_VCC33
A_VCC33
A_VCC33
A_VCC33
VCC33 VCC33
AGNDAGND
AGND
AGNDAGND
AGND
AGND
AGNDAGND
AGND
AGND
AGND Title
Size Document Number Rev
Date: Sheet
of
AUDIO 1.1A
Altera Cyclone II Starter Board
A
421Tuesday, October 03, 2006
Title
Size Document Number Rev
Date: Sheet of
AUDIO 1.1A
Altera Cyclone II Starter Board
A
421Tuesday, October 03, 2006
Title
Size Document Number Rev
Date: Sheet of
AUDIO 1.1A
Altera Cyclone II Starter Board
A
421Tuesday, October 03, 2006
I2C ADDRESS READ IS 0x34
I2C ADDRESS WRITE IS 0x35
R8 680R8 680
BC3
0.1U
BC3
0.1U
TC23
100U/6V
TC23
100U/6V
C1
1U
C1
1U
TC21
100U/6V
TC21
100U/6V
C2
1U
C2
1U
R7 330R7 330
BC4
0.1U
BC4
0.1U
R11
47K
R11
47K
C5
1000P
C5
1000P
L
1
R
2
GND
3
NCR
4
NCL
5
J1 MICINJ1 MICIN
C3
1U
C3
1U
R12 0R12 0
L
1
R
2
GND
3
NCR
4
NCL
5
J2 LINEINJ2 LINEIN
BC2
0.1U
BC2
0.1U
TC22
100U/6V
TC22
100U/6V
R10
47K
R10
47K
R9
47K
R9
47K
R6
4.7K
R6
4.7K
R2
2K
R2
2K
R5
4.7K
R5
4.7K
BC1
0.1U
BC1
0.1U
R3
2K
R3
2K
BCLK
7
HPVDD
12
XTO
2
DCVDD
3
MBIAS
21
MICIN
22
RLINEIN
23
LLINEIN
24
MODE
25
CSB
26
SDIN
27
SCLK
28
ROUT
17
AVDD
18
AGND
19
VMID
20
LOUT
16
HPGND
15
RHPOUT
14
LHPOUT
13
XTI/MCLK
1
DGND
4
ADCLRCK
11
ADCDAT
10
DBVDD
5
CLKOUT
6
DACDAT
8
DACLRCK
9
U1
WM8731
U1
WM8731
R4 4.7KR4 4.7K
L
1
R
2
GND
3
NCR
4
NCL
5
J3 LINEOUTJ3 LINEOUT
R1 4.7KR1 4.7K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VGA_G0
VGA_G2
G
VGA_G3
VGA_B2
VGA_B3
VGA_B0
B
VGA_R3
VGA_R2
VGA_VSYNC
VGA_HSYNCH
V
VGA_R0
VGA_R1
VGA_G1
VGA_B1
R
VGA_G[0..3]
VGA_B[0..3]
VGA_HSYNC
VGA_R[0..3]
VGA_VSYNC
Title
Size Document Number Rev
Date: Sheet
of
VGA 1.1A
Altera Cyclone II Starter Board
A
521Tuesday, October 03, 2006
Title
Size Document Number Rev
Date: Sheet of
VGA 1.1A
Altera Cyclone II Starter Board
A
521Tuesday, October 03, 2006
Title
Size Document Number Rev
Date: Sheet of
VGA 1.1A
Altera Cyclone II Starter Board
A
521Tuesday, October 03, 2006
R
G
B
RG
BG
GG
GND
GND
HS
VS
R14 120R14 120
R13 120R13 120
1
2
3
45
6
7
8
RN3
2K
RN3
2K
1
2
3
4 5
6
7
8
RN2
1K
RN2
1K
1
2
3
45
6
7
8
RN1
2K
RN1
2K
5
9
4
8
3
7
2
6
1
17
16
10
11
12
13
14
15
10
11
6
1
5
15
J4
VGA
10
11
6
1
5
15
J4
VGA
1
2
3
45
6
7
8
RN5
2K
RN5
2K
1
2
3
4 5
6
7
8
RN4
1K
RN4
1K
1
2
3
4 5
6
7
8
RN6
1K
RN6
1K
