Document Number: 307013-003
Intel
®
I/O Controller Hub 7 (ICH7)
Family
Datasheet
— For the Intel
®
82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH,
82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U I/O
Controller Hubs
April 2007
2 Intel
®
ICH7 Family Datasheet
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®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
I/O Controller Hub 7 (ICH7) Family chipset component may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other
countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005–2007, Intel Corporation
Intel
®
ICH7 Family Datasheet 3
Contents
1 Introduction ............................................................................................................ 39
1.1 Overview ......................................................................................................... 42
1.2 Intel
®
ICH7 Family High-Level Component Differences ........................................... 50
2 Signal Description ...................................................................................................51
2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 55
2.2 PCI Express* (Desktop and Mobile Only) ..............................................................55
2.3 Platform LAN Connect Interface (Desktop and Mobile Only)..................................... 56
2.4 EEPROM Interface (Desktop and Mobile Only)........................................................ 56
2.5 Firmware Hub Interface (Desktop and Mobile Only)................................................ 56
2.6 PCI Interface .................................................................................................... 57
2.7 Serial ATA Interface (Desktop and Mobile Only) ..................................................... 59
2.8 IDE Interface.................................................................................................... 60
2.9 LPC Interface.................................................................................................... 62
2.10 Interrupt Interface ............................................................................................ 62
2.11 USB Interface ................................................................................................... 63
2.12 Power Management Interface.............................................................................. 64
2.13 Processor Interface............................................................................................66
2.14 SMBus Interface................................................................................................ 68
2.15 System Management Interface............................................................................ 68
2.16 Real Time Clock Interface................................................................................... 69
2.17 Other Clocks..................................................................................................... 69
2.18 Miscellaneous Signals ........................................................................................ 70
2.19 AC ’97/Intel
®
High Definition Audio Link............................................................... 71
2.20 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................... 72
2.21 Intel
®
Quick Resume Technology (Intel
®
ICH7DH Only) ......................................... 72
2.22 General Purpose I/O Signals ............................................................................... 72
2.23 Power and Ground............................................................................................. 74
2.24 Pin Straps ........................................................................................................ 76
2.24.1 Functional Straps ................................................................................... 76
2.24.2 External RTC Circuitry............................................................................. 78
3 Intel
®
ICH7 Pin States............................................................................................. 79
3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 79
3.2 IDE Integrated Series Termination Resistors..........................................................80
3.3 Output and I/O Signals Planes and States............................................................. 81
3.4 Power Planes for Input Signals ............................................................................ 90
4 Intel
®
ICH7 and System Clock Domains................................................................... 95
5 Functional Description............................................................................................. 99
5.1 PCI-to-PCI Bridge (D30:F0) ................................................................................ 99
5.1.1 PCI Bus Interface ................................................................................... 99
5.1.2 PCI Bridge As an Initiator ........................................................................ 99
5.1.2.1 Memory Reads and Writes..........................................................99
5.1.2.2 I/O Reads and Writes .............................................................. 100
5.1.2.3 Configuration Reads and Writes ................................................ 100
5.1.2.4 Locked Cycles......................................................................... 100
5.1.2.5 Target / Master Aborts............................................................. 100
5.1.2.6 Secondary Master Latency Timer............................................... 100
5.1.2.7 Dual Address Cycle (DAC) ........................................................ 100
5.1.2.8 Memory and I/O Decode to PCI................................................. 101
5.1.3 Parity Error Detection and Generation ..................................................... 101
5.1.4 PCIRST#............................................................................................. 101
4 Intel
®
ICH7 Family Datasheet
5.1.5 Peer Cycles..........................................................................................102
5.1.6 PCI-to-PCI Bridge Model ........................................................................102
5.1.7 IDSEL to Device Number Mapping...........................................................103
5.1.8 Standard PCI Bus Configuration Mechanism..............................................103
5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) (Desktop and Mobile Only) ..........103
5.2.1 Interrupt Generation .............................................................................103
5.2.2 Power Management...............................................................................104
5.2.2.1 S3/S4/S5 Support ...................................................................104
5.2.2.2 Resuming from Suspended State...............................................104
5.2.2.3 Device Initiated PM_PME Message .............................................104
5.2.2.4 SMI/SCI Generation.................................................................105
5.2.3 SERR# Generation................................................................................105
5.2.4 Hot-Plug..............................................................................................106
5.2.4.1 Presence Detection..................................................................106
5.2.4.2 Message Generation ................................................................106
5.2.4.3 Attention Button Detection .......................................................107
5.2.4.4 SMI/SCI Generation.................................................................107
5.3 LAN Controller (B1:D8:F0) (Desktop and Mobile Only) ..........................................108
5.3.1 LAN Controller PCI Bus Interface.............................................................108
5.3.1.1 Bus Slave Operation ................................................................109
5.3.1.2 CLKRUN# Signal (Mobile Only)..................................................110
5.3.1.3 PCI Power Management ...........................................................110
5.3.1.4 PCI Reset Signal......................................................................110
5.3.1.5 Wake-Up Events......................................................................111
5.3.1.6 Wake on LAN* (Preboot Wake-Up).............................................112
5.3.2 Serial EEPROM Interface........................................................................112
5.3.3 CSMA/CD Unit......................................................................................113
5.3.3.1 Full Duplex.............................................................................113
5.3.3.2 Flow Control ...........................................................................113
5.3.3.3 VLAN Support.........................................................................113
5.3.4 Media Management Interface .................................................................113
5.3.5 TCO Functionality .................................................................................114
5.3.5.1 Advanced TCO Mode ................................................................114
5.4 Alert Standard Format (ASF) (Desktop and Mobile Only) .......................................115
5.4.1 ASF Management Solution Features/Capabilities .......................................116
5.4.2 ASF Hardware Support ..........................................................................117
5.4.2.1 Intel
®
82562EM/EX .................................................................117
5.4.2.2 EEPROM (256x16, 1 MHz) ........................................................117
5.4.2.3 Legacy Sensor SMBus Devices ..................................................117
5.4.2.4 Remote Control SMBus Devices.................................................117
5.4.2.5 ASF Sensor SMBus Devices.......................................................117
5.4.3 ASF Software Support ...........................................................................118
5.5 LPC Bridge (w/ System and Management Functions) (D31:F0)...............................118
5.5.1 LPC Interface .......................................................................................118
5.5.1.1 LPC Cycle Types ......................................................................119
5.5.1.2 Start Field Definition................................................................119
5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR).....................................120
5.5.1.4 SIZE......................................................................................120
5.5.1.5 SYNC.....................................................................................121
5.5.1.6 SYNC Time-Out.......................................................................121
5.5.1.7 SYNC Error Indication ..............................................................121
5.5.1.8 LFRAME# Usage......................................................................122
5.5.1.9 I/O Cycles..............................................................................122
5.5.1.10 Bus Master Cycles ...................................................................122
5.5.1.11 LPC Power Management ...........................................................122
5.5.1.12 Configuration and Intel
®
ICH7 Implications.................................123
5.5.2 SERR# Generation................................................................................123
Intel
®
ICH7 Family Datasheet 5
5.6 DMA Operation (D31:F0).................................................................................. 124
5.6.1 Channel Priority ................................................................................... 124
5.6.1.1 Fixed Priority.......................................................................... 125
5.6.1.2 Rotating Priority ..................................................................... 125
5.6.2 Address Compatibility Mode................................................................... 125
5.6.3 Summary of DMA Transfer Sizes............................................................. 125
5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by
Words ................................................................................... 126
5.6.4 Autoinitialize........................................................................................ 126
5.6.5 Software Commands............................................................................. 126
5.7 LPC DMA (Desktop and Mobile Only) .................................................................. 127
5.7.1 Asserting DMA Requests........................................................................ 127
5.7.2 Abandoning DMA Requests .................................................................... 127
5.7.3 General Flow of DMA Transfers ............................................................... 128
5.7.4 Terminal Count .................................................................................... 128
5.7.5 Verify Mode ......................................................................................... 128
5.7.6 DMA Request Deassertion...................................................................... 129
5.7.7 SYNC Field / LDRQ# Rules..................................................................... 129
5.8 8254 Timers (D31:F0) ..................................................................................... 130
5.8.1 Timer Programming.............................................................................. 131
5.8.2 Reading from the Interval Timer............................................................. 132
5.8.2.1 Simple Read........................................................................... 132
5.8.2.2 Counter Latch Command.......................................................... 132
5.8.2.3 Read Back Command .............................................................. 132
5.9 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 133
5.9.1 Interrupt Handling................................................................................ 134
5.9.1.1 Generating Interrupts.............................................................. 134
5.9.1.2 Acknowledging Interrupts ........................................................ 134
5.9.1.3 Hardware/Software Interrupt Sequence ..................................... 135
5.9.2 Initialization Command Words (ICWx)..................................................... 135
5.9.2.1 ICW1 .................................................................................... 135
5.9.2.2 ICW2 .................................................................................... 136
5.9.2.3 ICW3 .................................................................................... 136
5.9.2.4 ICW4 .................................................................................... 136
5.9.3 Operation Command Words (OCW)......................................................... 136
5.9.4 Modes of Operation .............................................................................. 136
5.9.4.1 Fully Nested Mode................................................................... 136
5.9.4.2 Special Fully-Nested Mode........................................................ 137
5.9.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 137
5.9.4.4 Specific Rotation Mode (Specific Priority).................................... 137
5.9.4.5 Poll Mode............................................................................... 137
5.9.4.6 Cascade Mode ........................................................................ 138
5.9.4.7 Edge and Level Triggered Mode................................................. 138
5.9.4.8 End of Interrupt (EOI) Operations ............................................. 138
5.9.4.9 Normal End of Interrupt........................................................... 138
5.9.4.10 Automatic End of Interrupt Mode .............................................. 138
5.9.5 Masking Interrupts ............................................................................... 139
5.9.5.1 Masking on an Individual Interrupt Request................................ 139
5.9.5.2 Special Mask Mode.................................................................. 139
5.9.6 Steering PCI Interrupts ......................................................................... 139
5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 140
5.10.1 Interrupt Handling................................................................................ 140
5.10.2 Interrupt Mapping ................................................................................ 140
5.10.3 PCI / PCI Express* Message-Based Interrupts.......................................... 141
5.10.4 Front Side Bus Interrupt Delivery ........................................................... 141
5.10.4.1 Edge-Triggered Operation......................................................... 142
