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ARM920T_TRM1_S (ARM9 芯片文档)
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Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM DDI 0151C
ARM920T
(Rev 1)
Technical Reference Manual
ii Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DDI 0151C
ARM920T
Technical Reference Manual
Copyright © 2000, 2001 ARM Limited. All rights reserved.
Release Information
Proprietary Notice
Words and logos marked with
®
or
™
are registered trademarks or trademarks owned by ARM Limited, except
as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Figure 9-5 on page 9-12 reprinted with permission IEEE Std 1149.1-1990, IEEE Standard Test Access Port
and Boundary-Scan Architecture Copyright 2000, by IEEE. The IEEE disclaims any responsibility or liability
resulting from the placement and use in the described manner
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
ARM delivered this document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Change
31st January 2000 A First release
5th September 2000 B Second release
18th April 2001 C Third release
ARM DDI 0151C Copyright © 2000, 2001 ARM Limited. All rights reserved. iii
Contents
ARM920T Technical Reference Manual
Preface
About this document .................................................................................... xvi
Further reading ............................................................................................ xix
Feedback ...................................................................................................... xx
Chapter 1 Introduction
1.1 About the ARM920T ................................................................................... 1-2
1.2 Processor functional block diagram ............................................................ 1-3
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 About the ARM9TDMI programmer’s model ............................................... 2-3
2.3 CP15 register map summary ...................................................................... 2-5
Chapter 3 Memory Management Unit
3.1 About the MMU ........................................................................................... 3-2
3.2 MMU program accessible registers ............................................................. 3-4
3.3 Address translation ..................................................................................... 3-6
3.4 MMU faults and CPU aborts ..................................................................... 3-21
3.5 Fault address and fault status registers .................................................... 3-22
3.6 Domain access control .............................................................................. 3-23
3.7 Fault checking sequence .......................................................................... 3-25
Contents
iv Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DDI 0151C
3.8 External aborts ......................................................................................... 3-28
3.9 Interaction of the MMU and caches .......................................................... 3-29
Chapter 4 Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM
4.1 About the caches and write buffer .............................................................. 4-2
4.2 ICache ........................................................................................................ 4-4
4.3 DCache and write buffer ............................................................................. 4-9
4.4 Cache coherence ..................................................................................... 4-16
4.5 Cache cleaning when lockdown is in use ................................................. 4-19
4.6 Implementation notes ............................................................................... 4-20
4.7 Physical address TAG RAM ..................................................................... 4-21
4.8 Drain write buffer ...................................................................................... 4-22
4.9 Wait for interrupt ....................................................................................... 4-23
Chapter 5 Clock Modes
5.1 About ARM920T clocking ........................................................................... 5-2
5.2 FastBus mode ............................................................................................ 5-3
5.3 Synchronous mode ..................................................................................... 5-4
5.4 Asynchronous mode ................................................................................... 5-6
Chapter 6 Bus Interface Unit
6.1 About the ARM920T bus interface ............................................................. 6-2
6.2 Unidirectional AMBA ASB interface ............................................................ 6-3
6.3 Fully-compliant AMBA ASB interface ......................................................... 6-5
6.4 AMBA AHB interface ................................................................................ 6-20
6.5 Level 2 cache support and performance analysis .................................... 6-22
Chapter 7 Coprocessor Interface
7.1 About the ARM920T coprocessor interface ................................................ 7-2
7.2 LDC/STC .................................................................................................... 7-5
7.3 MCR/MRC .................................................................................................. 7-9
7.4 Interlocked MCR ....................................................................................... 7-11
7.5 CDP .......................................................................................................... 7-13
7.6 Privileged instructions ............................................................................... 7-15
7.7 Busy-waiting and interrupts ...................................................................... 7-17
Chapter 8 Trace Interface Port
8.1 About the ETM interface ............................................................................. 8-2
Chapter 9 Debug Support
9.1 About debug ............................................................................................... 9-2
9.2 Debug systems ........................................................................................... 9-3
9.3 Debug interface signals .............................................................................. 9-5
9.4 Scan chains and JTAG interface .............................................................. 9-11
9.5 The JTAG state machine .......................................................................... 9-12
9.6 Test data registers .................................................................................... 9-19
Contents
ARM DDI 0151C Copyright © 2000, 2001 ARM Limited. All rights reserved. v
9.7 ARM920T core clocks ............................................................................... 9-41
9.8 Clock switching during debug ................................................................... 9-42
9.9 Clock switching during test ........................................................................ 9-43
9.10 Determining the core state and system state ............................................ 9-44
9.11 Exit from debug state ................................................................................ 9-47
9.12 The behavior of the program counter during debug .................................. 9-50
9.13 EmbeddedICE macrocell .......................................................................... 9-53
9.14 Vector catching ......................................................................................... 9-60
9.15 Single-stepping ......................................................................................... 9-61
9.16 Debug communications channel ............................................................... 9-62
Chapter 10 TrackingICE
10.1 About TrackingICE .................................................................................... 10-2
10.2 Timing requirements ................................................................................. 10-3
10.3 TrackingICE outputs ................................................................................. 10-4
Chapter 11 AMBA Test Interface
11.1 About the AMBA test interface .................................................................. 11-2
11.2 Entering and exiting AMBA Test ............................................................... 11-3
11.3 Functional test ........................................................................................... 11-4
11.4 Burst operations ...................................................................................... 11-11
11.5 PA TAG RAM test ................................................................................... 11-12
11.6 Cache test ............................................................................................... 11-15
11.7 MMU test ................................................................................................. 11-19
Chapter 12 Instruction Cycle Summary and Interlocks
12.1 About the instruction cycle summary ........................................................ 12-2
12.2 Instruction cycle times ............................................................................... 12-3
12.3 Interlocks ................................................................................................... 12-6
Chapter 13 AC Characteristics
13.1 ARM920T timing diagrams ........................................................................ 13-2
13.2 ARM920T timing parameters .................................................................. 13-14
13.3 Timing definitions for the ARM920T Trace Interface Port ....................... 13-24
Appendix A Signal Descriptions
A.1 AMBA signals .............................................................................................. A-2
A.2 Coprocessor interface signals ..................................................................... A-5
A.3 JTAG and TAP controller signals ................................................................ A-7
A.4 Debug signals ........................................................................................... A-10
A.5 Miscellaneous signals ............................................................................... A-12
A.6 ARM920T Trace Interface Port signals ..................................................... A-13
Appendix B CP15 Test Registers
B.1 About the test registers ............................................................................... B-2
B.2 Test state register ....................................................................................... B-3
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