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  • winpacp.rar

    winpacp抓包获取MAC, pcap_compile()过滤使用,获取网卡速率

    2019-09-19
    9
  • The C11 and C++11 Concurrency Model.pdf

    The advent of pervasive concurrency has caused fundamental design changes throughout computer systems. In a bid to offer faster and faster machines, designers had been pro- ducing hardware with ever higher clock frequencies, leading to extreme levels of power dissipation. This approach began to give diminishing returns, and in order to avoid phys- ical limitations while maintaining the rate of increase in performance, processor vendors embraced multi-core designs. Multi-core machines contain several distinct processors that work in concert to complete a task. The individual processors can operate at lower fre- quencies, while collectively possessing computing power that matches or exceeds their single core counterparts. Unfortunately, multi-core processor performance is sensitive to the sort of work they are given: large numbers of wholly independent tasks are ideal, whereas monolithic tasks that cannot be split up are pathological. Most tasks require some communication between cores, and the cost of this communication limits perfor-mance on multi-core systems.

    2018-04-21
    0
  • Gcc连接动态库

    Communication between cores in mainstream multi-core machines is enabled by a shared memory. To send information from one core to another, one core writes to mem- ory and the other reads from memory. Unfortunately, memory is extremely slow when compared with computation. Processor designers go to great lengths to reduce the la- tency of memory by introducing caches and buffers in the memory system. In the design of such a memory, there is a fundamental choice: one can design intricate protocols that hide the details, preserving the illusion of a simple memory interface while introducing communication delay, or one can allow memory accesses to appear to happen out of order, betraying some of the internal workings of the machine. Mainstream processor vendors all opt for the latter: ARM, IBM’s Power, SPARC-TSO, and Intel’s x86 and Itanium architectures allow the programmer to see strange behaviour at the interface to memory in order to allow agressive optimisation in the memory subsystem.

    2018-04-21
    0
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