IHI_0070_C_a_System_Memory_Management_Unit_Arm_Architecture_Specification.pdf

arm smmu spec. A System Memory Management Unit (SMMU) performs a task that is analogous to that of an MMU in a PE, translating addresses for DMA requests from system I/O devices before the requests are passed into the system interconnect. It is active for DMA only. Traffic in the other direction, from the system or PE to the device, is managed by other means – for example, the PE MMUs.

HI0069E_gic_architecture_specification_v3.pdf

The GICv3 architecture is designed to operate with Armv8-A and Armv8-R compliant processing elements, PEs. The Generic Interrupt Controller (GIC) architecture defines: • The architectural requirements for handling all interrupt sources for any PE connected to a GIC. • A common interrupt controller programming interface applicable to uniprocessor or multiprocessor systems

GICv3_Software_Overview_Official_Release_B.pdf

This document provides a software focused overview of the features of GICv3, and describes the operation of a GICv3 compliant interrupt controller. It is also a primer on how to configure a GICv3 interrupt controller for use in a bare metal environment. This document compliments the ARM® Generic Interrupt Controller Architecture Specification GIC architecture version 3.0 and 4.0. It is not a replacement or alternative. Refer to the ARM® Generic Interrupt Controller Architecture Specification GIC architecture version 3.0 and 4.0 for detailed descriptions of registers and behaviors.