• Pipelined SAR ADC with Loading-Free Architecture.pdf

    The pipeline SAR ADC with loading - Free architecture

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    2019-09-30
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  • Custom IC design.rar

    Cadence EDA design tools white paper for advance design

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    2019-09-30
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  • PLL COurse.rar

    PLL Application 鎖相迴路在眾多領域有應用,如無線通信、數位電視、廣播等。具體的應用範圍包括但不限於: 無線通信系統收發模塊 (Transceiver) 數據及時鐘恢復電路 (Clock and Data Recovery - CDR) 頻率綜合電路 (Frequency synthesizer) 跳頻通信 (Frequency-hopping spread spectrum - FHSS) 數位電視接收機

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    2019-09-30
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  • Design of high speed Energy-Efficient SAR ADC_劉純成.pdf

    This dissertation proposes three circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-of-concept prototypes, the proposed techniques are able to improve the operating speed and achieve excellent energy efficiency. The proposed techniques and chip measurement results are sketched as follows: The first technique is a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total sampling capacitance are reduced by about 81.3% and 50%, respectively. A 10-bit, 50-MS/s SAR ADC with the proposed monotonic capacitor switching procedure is implemented in a 0.13-μm 1P8M CMOS technology. The prototype ADC consumes 0.92 mW from a 1.2-V supply, and the effective number of bit (ENOB) is 8.48 bits. The resulting figure of merit (FOM) is 52 fJ/conversion-step. However, the signal-dependent offset caused by the variation of the input common-mode voltage degrades the linearity of ADC. We proposed an improved comparator design to avoid the linearity degradation. Besides, to avoid a clock signal with frequency higher than sampling rate, we used an asynchronous control circuit to internally generate the necessary control signals. The revised prototype is also implemented in a 0.13-μm 1P8M CMOS technology. It consumes 0.826 mW from a 1.2-V supply and achieves an ENOB of 9.18 bits. The resultant FOM is 29 fJ/conversion-step.

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  • Easily-Integrated and Energy-Efficient Design Techniques for SAR ADC

    Abstract: This dissertation presents four circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-of-concept prototypes, the proposed techniques are able to reduce the design overhead of the front-end and reference buffer and improve the ADC performance. The proposed techniques and their associated chip measurement results are sketched as follows: The first technique is to develop a low input capacitance architecture for SAR ADCs. A 10-bit prototype is fabricated in 0.13-μm CMOS process. Compared with conventional successive approximation ADCs, the proposed ADC can reduce the input capacitance to 1.2 pF for 10-bit resolution. At 12 MS/s and 1.2-V supply, this ADC consumes 0.32 mW and achieves an SNDR of 50.89 dB, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.

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    2019-09-30
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