IEEE低通滤波精典
LPF IEEE Abstract—This paper proposes a filtered-sequence phase-locked loop (FSPLL) structure for detection of the positive sequence in three-phase systems. The structure includes the use of the Park transformation and moving average filters (MAF). Performance of the MAF is mathematically analyzed and represented in Bode diagrams. The analysis allows a proper selection of the window width of the optimal filter for its application in the dq transformed variables. The proposed detector structure allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF eliminates completely any oscillation multiple of the frequency for which it is designed; thus, this algorithm is not affected by the presence of imbalances or harmonics in the electrical grid. Furthermore, the PLL includes a simple-frequency detector that makes frequency adaptive the frequency depending blocks. This guarantees the proper operation of the FSPLL under large frequency changes. The performance of the entire PLL-based detector is verified through simulation and experiment. It shows very good performance under several extreme grid voltage conditions.
