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  • CMOS MN34220 摄像机设计原理图

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  • MA245x_DB-R_v1.02_Spetek.pdf

    Table of Contents 1 Myriad 2 Platorm...................................................................................................................6 1.1 Overview......................................................................................................................................6 1.2 Hardware Summary.....................................................................................................................7 1.3 IC nomenclature...........................................................................................................................8 2 Top-Level System....................................................................................................................9 2.1 MA245x Bus Interconnect...........................................................................................................9 2.2 Boot Operanon..........................................................................................................................16 2.3 Secure Boot................................................................................................................................46 3 CPU Sub-system....................................................................................................................52 3.1 LEON4 – High-performance SPARC V8 32-bit Processor............................................................52 3.2 GRFPU – High-performance IEEE-754 Floanng-point unit.........................................................74 3.3 DSU4 – LEON4 Hardware Debug Support Unit..........................................................................81 3.4 Leon L2C – Level 2 Cache controller for the Leons....................................................................98 3.5 Interrupt Controller.................................................................................................................114 3.6 Timers......................................................................................................................................123 3.7 Clock, Power and Reset Control...............................................................................................131 3.8 AON block................................................................................................................................159 3.9 Retennon Register...................................................................................................................163 3.10 Temperature Sensors.............................................................................................................166 3.11 USB Controller........................................................................................................................170 3.12 USB PHY.................................................................................................................................424 3.13 Mobile Storage/SDIO.............................................................................................................476 3.14 Gigabit Ethernet Media Access Controller (MAC).................................................................644 3.15 AHB_DMA..............................................................................................................................659 3.16 APB_I2S..................................................................................................................................809 3.17 APB_I2C..................................................................................................................................847 3.18 APB_SPI..................................................................................................................................936 3.19 APB_UART............................................................................................................................1011 3.20 GPIO Interface......................................................................................................................1075 3.21 JTAG Interface......................................................................................................................1097 4 SHAVE Protessor Core.......................................................................................................1099 4.1 Local Address Space Control Unit..........................................................................................1099 4.2 L1 Caches...............................................................................................................................1100 4.3 Translanon Lookaside Bufer..................................................................................................1103 4.4 Interrupt Request Support.....................................................................................................1105 4.5 Register Files..........................................................................................................................1105 4.6 SHAVE Instrucnon Set Architecture.......................................................................................1124 4.7 Register Interface...................................................................................................................1320 4.8 SHAVE Debug & Control Unit (DCU)......................................................................................1326 5 Protessor Memory Blotk (PMB)........................................................................................1347 5.1 CMX Memory System............................................................................................................1347 5.2 CMX FIFO...............................................................................................................................1358 Intel® Movidius™ Confdennal 3 MA245x-DB-1.02 Released to Shanghai Spetek Information Technology Development Co., Ltd. Per Intel CNDA# cnda023213 5.3 CMX DMA Controller.............................................................................................................1364 5.4 Bicubic Filter..........................................................................................................................1387 5.5 Myriad 2 Mutex Controller....................................................................................................1411 5.6 SHAVE L2 Cache.....................................................................................................................1417 6 DRAM Subsystem..............................................................................................................1430 6.1 DDR Controller.......................................................................................................................1430 6.2 DDR PHY.................................................................................................................................1485 7 Media Subsystem (MSS)....................................................................................................1672 7.1 Overview................................................................................................................................1672 7.2 Feature Set.............................................................................................................................1672 7.3 Block diagrams.......................................................................................................................1673 7.4 Architecture...........................................................................................................................1673 7.5 Sofware Driver Notes............................................................................................................1681 7.6 Register Interface...................................................................................................................1688 7.7 Camera Interface...................................................................................................................1703 7.8 LCD Controller / Video Out....................................................................................................1738 7.9 NAL.........................................................................................................................................1793 7.10 MIPI Controller.....................................................................................................................1822 7.11 MIPI D-PHY Bidir 2L..............................................................................................................1889 7.12 Streaming Image Processing Pipeline Accelerators.............................................................1994 7.13 Accelerator Memory Controller...........................................................................................2187 8 Power Management..........................................................................................................2195 8.1 Power Management Features...............................................................................................2195 8.2 Power Island defninons........................................................................................................2197 8.3 Power states...........................................................................................................................2199 8.4 Core voltages.........................................................................................................................2204 8.5 Dynamic Frequency scaling support......................................................................................2204 9 Elettrital...........................................................................................................................2206 9.1 Overview................................................................................................................................2206 9.2 Chip Operanng Condinons.....................................................................................................2206 9.3 GPIO Pins................................................................................................................................2208 9.4 Operanng ranges....................................................................................................................2219 10 Patkage...........................................................................................................................2220 10.1 Overview..............................................................................................................................2220 10.2 Package Thermal Informanon..............................................................................................2222 10.3 Solder Refow Profle...........................................................................................................2222 10.4 Moisture Sensinvity Level (MSL)..........................................................................................2223 10.5 Restricnon On Hazardous Substances (ROHS) compliance.................................................2223 10.6 VFBGA Package Ball out.......................................................................................................2224 10.7 BGA Package Outline...........................................................................................................2225 11 Movidius Produtt Ordering Informaton..........................................................................2226 11.1 Product Ordering Codes......................................................................................................2226 11.2 Product Ordering Opnons....................................................................................................2226 11.3 Minimum Order Requirements...........................................................................................2227 Intel® Movidius™ Confdennal 4 MA245x-DB-1.02 Released to Shanghai Spetek Information Technology Development Co., Ltd. Per Intel CNDA# cnda023213 11.4 MA245x Delivery Tray..........................................................................................................2228

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  • FPAG开发完全攻略(上)

    前言 2 第一章、为什么工程师要掌握FPGA开发知识? 5 第二章、FPGA基本知识与发展趋势 7 2.1 FPGA结构和工作原理 7 2.1.1 梦想成就伟业 7 2.1.2 FPGA结构 8 2.1.3 软核、硬核以及固核的概念 15 2.1.4 从可编程器件发展看FPGA未来趋势 15 第三章、FPGA主要供应商与产品 17 3.1.1 赛灵思主要产品介绍 17 第四章、FPGA开发基本流程 29 4.1 典型FPGA开发流程与注意事项 29 4.2 基于FPGA的SOC设计方法 32 基于FPGA的典型SOC开发流程为 32 第五章、FPGA实战开发技巧 33 5.1 FPGA器件选型常识 33 5.1.1器件的供货渠道和开发工具的支持 33 5.1.2 器件的硬件资源 33 5.1.3 电气接口标准 34 5.1.4 器件的速度等级 35 5.1.5 器件的温度等级 35 5.1.6 器件的封装 35 5.1.7 器件的价格 35 5.2 如何进行FPGA设计早期系统规划 36 5.3.综合和仿真技巧 37 5.3.1 综合工具XST的使用 37 5.3.2 基于ISE的仿真 42 5.3.3 和FPGA接口相关的设置以及时序分析 45 5.3.4 综合高手揭秘XST的11个技巧 51 5.4 大规模设计带来的综合和布线问题 52 5.5 FPGA相关电路设计知识 54 5.5.1 配置电路 54 5.5.2 主串模式——最常用的FPGA配置模式 56 5.5.3 SPI串行Flash配置模式 58 5.5.4 从串配置模式 62 5.5.5 JTAG配置模式 63 5.5.6 System ACE配置方案 64 5.6 大规模设计的调试经验 68 5.6.1 ChipScope Pro组件应用实例 68 5.7 FPGA设计的IP和算法应用 74 5.7.1 IP核综述 74 5.7.2 FFT IP核应用示例 75 5.8 赛灵思 FPGA的专用HDL开发技巧 79 5.8.1 赛灵思 FPGA的体系结构特点 79 5.8.2 赛灵思 FPGA 芯片专用代码风格 79 ISE与EDK开发技巧之时序篇 83 5.10 新一代开发工具ISE Design Suit10.1介绍 85 5.10.1 ISE Design Suit10.1综述 85 5.10.2 ISE Design Suit 10.1的创新特性 85 5.11 ISE与第三方软件的配合使用技巧 92 5.11.1 Synplify Pro软件的使用 92 5.11.2 ModelSim软件的使用 99 5.11.3 Synplify Pro、ModelSim和ISE的联合开发流程 104 5.11.4 ISE与MATLAB的联合使用 105 5.12 征服FPGA低功耗设计的三个挑战 108 5.13 高手之路——FPGA设计开发中的进阶路线 111

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  • FPAG开发完全攻略(下)

    前言 2 第六章、FPGA应用开发实例 4 6.1 如何克服FPGA I/O引脚分配挑战 4 6.2 用 Xilinx XtremeDSP 视频入门套件加速 FPGA 上的视频开发 10 6.3用 Spartan-3A DSP 器件实现汽车应用中的块匹配 14 6.4 利用 CoolRunner-II CPLD 设计 GPS 系统 20 6.5 利用赛灵思 EDK工具和IP设计多处理器SOC 23 6.6 利用JTAG链进行更为精确的系统级和芯片级功率分析和热分析 27 6.7 识别和解决赛灵思FPGA设计中的时序问题 34 第七章、FPGA设计百问 40 第八章、FPGA开发资源总汇 78 第九章、编委信息与后记 79

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  • FPAG开发完全攻略

    对FPGA开发很有帮助 FPGA的结构概述:对 PROM EPROM E2PROM 熟悉的人都知道这些可编程器件的可编程原理是通过加高压或紫外线导致 三极管或 MOS 管内部的载流子密度发生变化 实现所谓的可编程 但是这些器件或只能实现单次可编程或编 程状态难以稳定 FPGA 则不同 它采用了逻辑单元阵列 LCA Logic Cell Array 这样一个新概念 内部包括可 配置逻辑模块CLB Configurable Logic Block 输出输入模块IOB Input Output Block 和内部连线 Interconnect 三个部分 FPGA 的可编程实际上是改变了 CLB 和 IOB 的触发器状态 这样 可以实现多次重复的编程由于 FPGA 需 要被反复烧写 它实现组合逻辑的基本结构不可能像 ASIC 那样通过固定的与非门来完成 而只能采用一种易 于反复配置的结构 查找表可以很好地满足这一要求 目前主流 FPGA 都采用了基于 SRAM 工艺的查找表结构 也有一些军品和宇航级 FPGA 采用 Flash 或者熔丝与反熔丝工艺的查找表结构 通过烧写文件改变查找表内容 的方法来实现对 FPGA 的重复配置 ">对FPGA开发很有帮助 FPGA的结构概述:对 PROM EPROM E2PROM 熟悉的人都知道这些可编程器件的可编程原理是通过加高压或紫外线导致 三极管或 MOS 管内部的载流子密度发生变化 实现所谓的可编程 但是这些器件或只能实现单

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  • 德国MK项目电调代码V0.36

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  • C8051F全系列样列程序源代码.rar

    C8051F全系列样列程序源代码 ADC Comparators Oscillators PortIO SPI UART Blinky DAC Interrupts PCA SMBus Timers Watchdog

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  • 人工智能:一种现代方法 (第2版)_部分2

    人工智能基础课程。强烈推荐! 第一部分:人工智能 第二部分:问题求解 第三部分:知识与推理 第四部分:规划 第五部分:不确定知识与推理

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  • 人工智能:一种现代方法 (第2版)_部分1

    人工智能基础课程。强烈推荐! 第一部分:人工智能 第二部分:问题求解 第三部分:知识与推理 第四部分:规划 第五部分:不确定知识与推理

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