Marvell的8口以太网交换芯片88E6085的datasheet文档。
The Marvell® 88E6085 device is a single chip integrated 10-port Fast Ethernet switch. This device supports ‘Best-in-Class’ Quality of Service (QoS) and the
highest ‘real-world’ performance. It is uniquely
designed for SOHO router and gateway applications.
This device contains eight 10BASE-T/100BASE-TX
transceivers (PHYs) and two MII ports. The 88E6085
device is designed to work in all environments. True
Plug-and-Play is supported with Auto-Crossover,
Auto-Negotiation, and Auto-Polarity in the PHYs,
along with bridge loop prevention (using Port States).
The 88E6085 contains ten independent 802.3 media
access controllers (MACs), a high-speed, non-blocking four traffic class QoS switch fabric that uses the
unique patented Marvell Dynamic Queue Limit architecture. The QoS architecture switches packets into
one of four traffic class queues based upon Port, IEEE
802.1p, IPv4 Type of Service (TOS) or Differentiated
Services (Diff-Serv), IPv6 Traffic Class, 802.1Q VLAN
ID, DA MAC address or SA MAC address. The
devices also contain a high-performance address
lookup engine with support for up to 2K active nodes,
and a 1 Mbit frame buffer memory. Back-pressure and
Pause frame-based flow control schemes are included
to support zero packet loss under temporary traffic
congestion. The MAC units in the devices comply fully
with the applicable sections of IEEE 802.3.
The two MII interfaces support a direct connection to
Management or Router CPUs with integrated MACs.
Both interfaces support MII-PHY mode or MII-MAC
mode. These interfaces, along with BPDU handling for
IEEE 802.1D Spanning Tree Protocol, 802.1w Rapid
Spanning Tree, 802.1s Multiple VLAN Spanning Tree,
programmable per-port VLAN configurations, 802.1Q
and Port States, support fully managed switches and
truly isolated WAN vs. LAN firewall applications. The
device supports 64 802.1Q VLAN IDs which can be
enabled on a per port basis. Three levels of 802.1Q
security is supported with error frame trapping and logging.
The 88E6085 supports multiple address databases
which allows packet routing without modification of the
MAC address. This allows the same MAC address to
exist multiple times in the MAC Address database with
multiple port mappings, to completely isolate the WAN
from the LAN database.
The integrated PHYs in the 88E6085 are designed
with the Marvell® cutting-edge mixed-signal processing technology for digital implementation of adaptive
equalization and clock data recovery. Special power
management techniques are used to facilitate low
power dissipation and high port count integration. Both
the PHY and MAC units in the 88E6085 comply fully
with the applicable sections of IEEE 802.3, IEEE
802.3u, and IEEE 802.3x standards
