线阵ccd 驱动程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity zuizhog is
port(clock: in std_logic;
    SP:out std_logic;
RS:out std_logic;
CP:out std_logic;
A:out std_logic;
A1:out std_logic;
A2:out std_logic;
B:out std_logic;
B1:out std_logic;
B2:out std_logic;
SH:out std_logic;
SH1:out std_logic;
SH2:out std_logic);
end;

architecture one of zuizhog is
signal counter1:integer range 0 to 2;
signal counter2:integer range 0 to 7;
signal counter3:integer range 0 to 23;
signal counter4:integer range 0 to 1391;
signal counter6:integer range 0 to 11;
signal counter7:integer range 0 to 11;
signal counter8:integer range 0 to 2783;

signal temp1,temp2:std_logic;

signal clk1,clk2,clk3,clk4,clk5,clk6,clk7,clk8,clk9,clk11,clk12,clk13,clk14,clk15,clk16,clk17,clk18,clk19,clk21,clk37,clk38,clk39,clk40,clk41,clk42,clk43,clk44,clk60,clk61,clk62,clk63,clk64,clk65,clk66,clk67,clk68,clk69,clk70,y,x,m,n:std_logic;

begin
process(clock)
begin
if rising_edge(clock) then
if  counter1=2 then
counter1<=0;
temp1<=not temp1;
else 
counter1 <=counter1+1;
end if;
end if;
if falling_edge(clock) then
 if counter1 =1 then
temp2<=not temp2;
end if;
end if;
end process;

clk1<=temp1 xor temp2;

process(clk1)
begin
if falling_edge(clk1) then
  if counter2=7 then
 counter2<=0;
else
 counter2<=counter2 + 1;
end if;