十进制计数的数码管滚动显示(VHDL源程序)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-----实体count10的说明
ENTITY COUNT10 IS
PORT(CLK:IN STD_LOGIC;
     Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
     SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY COUNT10;
-----实体count10的结构体art的说明
ARCHITECTURE ART OF COUNT10 IS
SIGNAL CNTOUT:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL S:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL FLAG:STD_LOGIC;
---------------------------------------------------------
 BEGIN
 P1: PROCESS(CLK,S,FLAG)          --进程开始
     BEGIN
     IF(CLK'EVENT AND CLK='1') THEN --检测clk高电平
       IF CNTOUT="1001"THEN        --该段为计数段
           CNTOUT<="0000";
       ELSE
       CNTOUT<=CNTOUT+1;
       END IF;
----------------------------------------------------------
       IF FLAG='1' THEN
          S<=S+1;
       ELSE
          S<=S-1;
       END IF;