“数字集成电路——电路、系统与设计”部分课后问题及答案资源-CSDN文库

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数字集成电路设计

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07微电子数字集成电路设计.rar （11个子文件）

07微电子数字集成电路设计

chapter_5_ex_sol.pdf 271KB

chapter7_ex.pdf 268KB

chapter11_ex.pdf 72KB

chapter1_ex.pdf 7KB

chapter6_ex.pdf 3.08MB

chapter3_ex.pdf 211KB

chapter4_ex.pdf 51KB

chapter5_ex.pdf 102KB

chapter10_ex.pdf 142KB

chapter6_ex_sol.pdf 3.76MB

chapter_10_ex_sol.pdf 650KB

1 Chapter 6 Problem Set

Chapter 6

PROBLEMS

1. [E, None, 4.2] Implement the equation X = ((A + B) (C + D + E) + F) G using complemen-

tary CMOS. Size the devices so that the output resistance is the same as that of an inverter

with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and

best equivalent pull-up or pull-down resistance?

Solution

Rewriting the output expression in the form X = ((A + B) (C + D + E) + F) G = ((AB +

CDE)F) + G allows us to build the pulldown network by inspection (parallel devices imple-

ment an OR, and series devices implement an AND). The pullup network is the dual of the

pulldown network.

The plot shows sizes that meet the requirement - in the worst case, the output resistance

of the circuit matches the output resistance of an inverter with NMOS W/L=2 and PMOS

W/L=6.

The worst case pull-up resistance occurs whenever a single path exists from the output

node to Vdd. Examples of vectors for the worst case are ABCDEFG=1111100 and 0101110.

The best case pull-up resistance occurs when ABCDEFG=0000000.

The worst case pull-down resistance occurs whenever a single path exists from the out-

put node to GND. Examples of vectors for the worst case are ABCDEFG=0000001 and

0011110.

The best case pull-down resistance occurs when ABCDEFG=1111111.

2. Implement the following expression in a full static CMOS logic fashion using no more than

10 transistors:

Solution

D E

2424

24 2424

YAB⋅()ACE⋅⋅()DE⋅()DCB⋅⋅()+++=

2 Chapter 6 Problem Set

The circuit is given in the next figure.

3. Consider the circuit of Figure 6.1.

a. What is the logic function implemented by the CMOS transistor network? Size the NMOS

and PMOS devices so that the output resistance is the same as that of an inverter with an

NMOS W/L = 4 and PMOS W/L = 8.

Solution

The logic function is :. The transistor sizes are given in the figure

above.

b. What are the input patterns that give the worst case t

pHL

and t

pLH

. State clearly what are the

initial input patterns and which input(s) has to make a transition in order to achieve this

maximum propagation delay. Consider the effect of the capacitances at the internal nodes.

Solution

The worst case t

pHL

happens when the internal node capacitances (Cx2 and Cx3) are

charged before the high to low transition. The initial states that can cause this are:

ABCD=[1010, 1110, 0110]. The final state is one of: ABCD=[1011, 0111].

Figure 6.1 CMOS combinational logic gate.

W/L=12

W/L=8

W/L=16

Cx2

Cx3

Cx1

YAB+()CD=

Digital Integrated Circuits - 2nd Ed 3

The worst case t

pLH

happens when Cx1 is charged before the low to high transition. The

input pattern that can cause this is: ABCD=[0111] =>[0011].

c. Verify part (b) with SPICE. Assume all transistors have minimum gate length (0.25µm).

Solution

The two cases are shown below.

d. If P(A=1)=0.5, P(B=1)=0.2, P(C=1)=0.3 and P(D=1)=1, determine the power dissipation

in the logic gate. Assume V

=2.5V, C

out

=30fF and f

clk

=250MHz.

Solution

Since D is always 1, the circuit implements the following function .

(A+B)=1

= P

A=0

= 0 = 0.5*(1-0.2) = 0.4,

(A+B)=0

= 1 - 0.4 = 0.6,

Y = 0

= P

(A+B) = 1

= 1 = 0.6*0.3 = 0.18

Y = 1

= 1 - 0.18 = 0.82

Y = 0 =>1

= 0.18*0.82 = 0.1476

So Pdyn = P

Y = 0 =>1

out

clk

= (0.1476)(30.10

-15

)(2.5

)(250.10

) = 6.92W.

4. [M, None, 4.2] CMOS Logic

a. Do the following two circuits (Figure 6.4) implement the same logic function? If yes, what

is that logic function? If no, give Boolean expressions for both circuits.

Figure 6.2 Best and worst t

pHL

Figure 6.3 Best and worst t

pLH

YAB+()C=

4 Chapter 6 Problem Set

Solution

Yes, they implement the same logic function :

F = (ABCD + E) = (A + B + C + D).E

b. Will these two circuits’ output resistances always be equal to each other?

Solution

c. Will these two circuits’ rise and fall times always be equal to each other? Why or why not?

Solution

No. Circuit B appears optimized for the case where the transistor with input E is on the

critical path since it is closer to the output node than in circuit A. Therefore, if input E arrives

later, circuit B will be faster than circuit A since the internal node will already be charged and

only the output capacitance needs to be switched. Even if we assume, all inputs arrive at the

same time, however, the two circuits rise and fall times will not be equal to each other. Con-

sider an input combination where E,A,B,C,D are all low. Circuit A has only one body-

affected device while circuit B has four. Since the associated rise in V

and fall in output resis-

tance affects only one resistor in circuit A, but four parallel resistors in circuit B, we expect a

difference in the timing waveforms.

5. [E, None, 4.2] The transistors in the circuits of the preceding problem have been sized to give

an output resistance of 13 kΩ for the worst-case input pattern. This output resistance can vary,

however, if other patterns are applied.

a. What input patterns (A–E) give the lowest output resistance when the output is low? What

is the value of that resistance?

Solution

The lowest output resistance is obtained when all inputs (A, B, C, D and E) are equal to

1. In that case, the output resistance is the parallel of the resistance of a nMOS of width 1,

with a series of four equal nMOS of width 4. Both combinations have the same resistance,

equal to the worst-case output resistance, 13 k. Then the output resistance, in this case, is

half this value, 6.5 k.

b. What input patterns (A–E) give the lowest output resistance when the output is high? What

is the value of that resistance?

Circuit A Circuit B

Figure 6.4 Two static

CMOS gates.

Ω

Digital Integrated Circuits - 2nd Ed 5

Solution

The lowest output resistance is obtained when all inputs are equal to zero. Each of the

pMOS have the same width, so all of them have the same resistance. The worst case resis-

tance happens when only one of the inputs (A, B, C or D) is equal to 0 while all the rest are

equal to 1. The output resistance in that case is the series of the resistance of two of the pMOS

and it is equal to 13 k. Then, each of the pMOS has an output resistance equal to 6.5 k.

The output resistance is equal to the series of one of these resistance with the parallel of four

of the same resistnaces. Then, the minimum output resistance is 6.5 k + 6.5 k/4 =

8.125 k.

6. [E, None, 4.2] What is the logic function of circuits A and B in Figure 6.5? Which one is a

dual network and which one is not? Is the nondual network still a valid static logic gate?

Explain. List any advantages of one configuration over the other.

Solution

Both circuits A and B implement the XOR logic function. Circuit A is a dual network

because the pull up network is dual with the pull down network.

However, circuit B is still a valid static logic gate, because for any combination of the

inputs, there is either a low resistance path from V

or ground to the output. Circuit B has an

extra advantage. The internal node capacitances are less compared to Circuit A, which make

it faster than Circuit A.

7. [E, None, 4.2] Compute the following for the pseudo-NMOS inverter shown in Figure 6.6:

a. V

and V

Solution

To find V

, set V

to 0, because V

is likely to be below V

for the NMOS. If

=0, then M

is off, so the PMOS pulls the output all the way to the rail. So,

=2.5V.

To find V

, set V

= V

= 2.5V. The NMOS is all the way on, but so is the PMOS.

To find V

, we can write a current balancing equation at the output node: I

=0. First,

we must determine the region of operation for each device. We can assume that V

= V

for the NMOS is less than V

DSAT

, so the NMOS is in the linear region. V

for the PMOS will

be more negative than V

DSAT

, and V

GTp

= -2.1, so the PMOS is velocity saturated. The equa-

tion is therefore:

Plugging in numbers (process parameters such as V

DSAT

appear in tables in previous

chapters) gives:

Ω Ω

Ω

A B

A A

Circuit A

A B

A A

Circuit B

Figure 6.5 Two logic functions.

----- V

DSAT

0.5V

DSAT

–()1 λV

+()⋅⋅⋅⋅k'

----- V

0.5V

–()1 λV

+()⋅⋅⋅⋅+0=

评论收藏

内容反馈

yyaa00356551

2013-05-08

非常感谢，觉得很不错
ydcr168

2013-05-29

谢谢分享了。不全，但是有点算一点了。
润物细无声_pro

2013-11-27

谢谢分享了。不是很全，，，但是有点算一点了。
xiaolingyun

2016-04-14

答案不全，不过很好了，多谢
小旭同学A0000

2013-03-10

答案是正确的，但是不太全，可也算包含了这本书的重点了

前往

页

clw89

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