ICN6201 Specification V0.8
- 1 -
ICN6201 Specification
MIPI
®
DSI BRIDGE TO FLATLINK
TM
LVDS
Revision 0.8
NOTICE NOTICENOTICENOTICENOTICE
This design and all of its related documentation constitutes valuable and confidential
property of Chipone Technology (Beijing) Co., Ltd. It is licensed for use as expressly
stated in the written license Agreement between Chipone Technology (Beijing) Co.,
Ltd and its customers. Any other use or redistribution of this design and all related
documentation is expressly prohibited.
This design and all related documentation have been released by Chipone Technology
(Beijing) Co., Ltd to its customers under a Non Disclosure Agreement (NDA).
Disclosure of this design outside of this agreement is expressly prohibited.
NOTICE NOTICENOTICENOTICENOTICE
ICN6201 Specification V0.8
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Revision History
Rev
Date
Author
Description
0.1
2013-04-03
Simon_Liu
Initial version
0.2
2013-04-12
Simon_Liu
1. add DC and AC characteristic, section 7
2. add MIPI Rx functions, section 6.1
0.3
2013-05-20
Simon_Liu
1. add section 6.4 & 6.5
0.4
2013-06-20
Simon_Liu
1. add diagram QFN40 and pin description.
0.5
2013-07-09
Simon_Liu
Only use QFN48 package
0.6
2013-07-09
Simon_Liu
Add QFN40 again
0.7
2013-07-18
Simon_Liu
1. add pin1 mark for diagram 4-1 & 4-2
2. add special e-pad for QFN48 diagram(8-3)
0.8
2013-07-18
Simon_Liu
Update QFN48 pin diagram
ICN6201 Specification V0.8
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Table of Contents
1 Introduction ................................................................................................................ - 5 -
1.1 Feature List ............................................................................................................................................ - 5 -
2 Functional Block Diagram ........................................................................................ - 6 -
3 System Application Diagram .................................................................................... - 7 -
4 Pin Diagram ................................................................................................................ - 8 -
5 Pin Description ........................................................................................................... - 9 -
6 Function Description ................................................................................................ - 11 -
6.1 MIPI Receiver ...................................................................................................................................... - 11 -
6.1.1 DSI Lane Merging ................................................................................................................................. - 11 -
6.1.2 DSI Pixel Stream Packets ...................................................................................................................... - 11 -
6.1.3 DSI Video Transmission sequence ........................................................................................................ - 13 -
6.2 LVDS Transmitter .............................................................................................................................. - 14 -
6.3 Bist mode .............................................................................................................................................. - 15 -
6.4 DSI access local registers .................................................................................................................... - 15 -
6.4.1 Write local registers .............................................................................................................................. - 15 -
6.4.2 Read local registers ............................................................................................................................... - 16 -
6.5 I2C access local registers .................................................................................................................... - 16 -
7 DC and AC Electrical Characteristics ................................................................... - 17 -
7.1 ABSOLUTE MAXIMUM RATING .................................................................................................. - 17 -
7.2 RECOMMENDED OPERATING CONDITIONS .......................................................................... - 17 -
7.3 Electrical Characteristics.................................................................................................................... - 18 -
7.3.1 MIPI DSI INTERFACE ........................................................................................................................ - 18 -
7.3.2 LVDS output ......................................................................................................................................... - 19 -
7.4 SWITCHING CHARACTERISTICS ............................................................................................... - 20 -
8 Package information ................................................................................................ - 22 -
8.1 QFN40 package ................................................................................................................................... - 22 -
8.2 QFN48 package ................................................................................................................................... - 23 -
ICN6201 Specification V0.8
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Table of figures
Figure 2-1 ICN6201 function block diagram ..................................................................................................... - 6 -
Figure 3-1 ICN6201 system application diagram ............................................................................................... - 7 -
Figure 4-1 ICN6201 QFN40 pin diagram (Top View) ....................................................................................... - 8 -
Figure 4-2 ICN6201 QFN48 pin diagram (Top View) ....................................................................................... - 8 -
Figure 6-1 DSI multi-lanes HS Transmission Example ................................................................................... - 11 -
Figure 6-2 DSI RGB666 Color format, Loosely Long Packet ......................................................................... - 12 -
Figure 6-3 DSI RGB666 Color format, Tightly Long Packet .......................................................................... - 12 -
Figure 6-4 DSI RGB888 Color format, Long Packet ....................................................................................... - 12 -
Figure 6-5 Non-Burst Mode with Sync Pulses ................................................................................................. - 13 -
Figure 6-6 Non-Burst Mode with Sync Events ................................................................................................ - 13 -
Figure 6-7 Burst mode ...................................................................................................................................... - 14 -
Figure 6-8 LVDS, 18-bit single port, VESA or JEITA format ......................................................................... - 14 -
Figure 6-9 LVDS, 24-bit single port, VESA format......................................................................................... - 14 -
Figure 6-10 24-bit single port, JEIDA format .................................................................................................. - 15 -
Figure 6-11 Bist mode pattern sequence .......................................................................................................... - 15 -
Figure 7-1 DSI HS UI timing definition ........................................................................................................... - 18 -
Figure 7-2 DSI HS/LP signaling and Contention Voltage................................................................................ - 19 -
Figure 7-3 LVDS output signaling ................................................................................................................... - 19 -
Figure 7-4 LVDS output data and clock timing ............................................................................................... - 21 -
Figure 7-5 Power on and RESET and ULPS timing ........................................................................................ - 21 -
Figure 8-1 QFN40 pin dimension ..................................................................................................................... - 22 -
Figure 8-2 QFN48 pin with special shape e-pad dimension ............................................................................. - 23 -
ICN6201 Specification V0.8
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1 Introduction
ICN6201 is a bridge chip which receives MIPI
®
DSI inputs and sends LVDS outputs.
MIPI
®
DSI supports up to 4 lanes and each lane operates at 1Gbps maximum; the totally maximum input
bandwidth is 4Gbps; and the MIPI defined ULPS(ultra-low-power state) is also supported. ICN6201 decodes
MIPI
®
DSI 18bepp RGB666 and 24bpp RGB888 packets.
The LVDS output 18 or 24 bits pixel with 25MHz to 154MHz, by VESA or JEIDA format.
ICN6201 support video resolution up to FHD (1920x1080) and WUXGA(1920x1200).
ICN6201 adopts QFN40 and QFN 48pins package.
1.1 Feature List
Supports MIPI
®
D-PHY Version 1.00.00 and MIPI
®
DSI Version 1.02.00.
Single Channel DSI Receiver with One, Two, Three and Four lanes configurable, each lanes operates up to
1Gbps.
Receives 18bpp RGB666 and 24bpp RGB888 packets defined by DSI.
Supports MIPI Low State, Ultra-Low Power State, Shut Down mode.
Single Channel LVDS with output clock range of 25MHz to 154MHz.
LVDS can be generated from MIPI HS clock or external reference clock.
Support LVDS clock with center spreading up to 2%, modulation 30KHz ~ 60KHz.
LVDS output with VESA or JEIDA format.
LVDS output pin order can be swapped flexible.
supply voltage: 1.8V.
provide I2C slave interface.
package: QFN40-pins with e-pad.
Package: QFN48-pins with e-pad.