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VC707 评估板手册。VC707 Evaluation Board for the Virtex-7 FPGA User Guide。
Date Version Revision 02/01/13 1.2 Updated vc707 Board Features Table 1-1, Virtex-7 XC7VX485T-2FFG1761C FPGA FPGA Configuration, USB JTAG, System Clock (SYscLK-P and SYSCLK_N), HDMI Video Output, IC BuS, Table 1-15, User I/O, Table 1-26, Power Management, and VITA 57.1 FMC2 HPC Connector(Partially Populated). Updated Figure 1-5, Figure 1-16, and Figure 1-25. Updated paragraph following Table 1-4, Figure 1-7, Figure 1-19, Figure 1-20, and Table 1-24. Added CPU Reset Pushbutton User rotary Switch User SMA, and PCle Form Factor Board TI Power System Cooling Added Table 1-27 and Table 1-28 Replaced PTDo8D021W with PTDO8D210W in Table 1-29. Added third paragraph to the introduction in Appendix C, master Constraints File listing. Added UG483 and removed NXP Semiconductors in Appendix F, Additional Resources. Added second paragraph to the introduction in Appendix G, Regulatory and Compliance Information 08/22/13 Updated Figure 1-2, Table 1-1, Table 1-12, Table 1-13, and Table 1-14. Updated Linear BPI Flash Memory. Replaced Master UCF Listing with Appendix C, Master Constraints File Listing 05/12/14 1.4 Updated disclaimer and copyright. In Table 1-27, changed U1 FPGA pin N39 to M39, B36 to a35 and b37 to a36 09/20/14 1.5 Added note to Table 1-1 and Table 1-27. Updated Table 1-7. Changed Net Name column heading to FHG1761 Placement in Table 1-11. Added I/o standard information to Table 1-4, Table 1-5, Table 1-8, Table 1-10, Table 1-18, Table 1-21, Table 1-23, Table 1-26 Table 1-27 and Table 1-28. Updated schematic net name for pins C34 and D35 in Table 1-27 and Table 1-28. Updated GTX Transceivers. Added Figure A-3 04/07/15 1.6 Added notes to Jitter Attenuated Clock and I2C Bus. Updated Table 1-24.Deleted redundant Figure B-2 FMC2 HPC Connector Pinout in Appendix B, VITA 57.1 FMC Connector Pinouts Added information for ordering the aTX power supply adapter cable 09/01/15 1.6.1 Made typographical edits. 03/26/16 1.7 Updated transceiver bank Mgt_ bank_119 in Table 1-1l Updated GPIO pin for CPU reset pushbutton switch in Table 1-26. Updated U1 FPGa pins for J37 FMC2 HPC pins B12, B13, B32, and B33 in Table 1-28. Added thickness information in Appendix E, Board pecifications 08/12/16 1.7.1 Made a typographical edit UG885(V171) August12,2016 www.xilinx.com VC707 Evaluation board VC707 Evaluation board www.xilinx.com UG885(V171) August12,2016 Table of Contents Revision History Chapter 1: Vc707 Evaluation Board Features Overview Additional Information 7 VC707 Board Features Feature descriptions ,···· Virtex-7 XC7VX485T-2FFG1761C FPGA DDR3 Memory·……… 14 Linear bPi Flash memory 18 USB 2.0 ULPI Transceiver 22 SD Card interface USB TAG :·····: ,,,,,,.25 Clock Generation........ GTX Transceivers PCI Express Endpoint Connectivity 5 SFP/SFP+ Module Connector ,,,,,39 10/100/1000 Tri-Speed ethernet phy .40 SGMII GTX Transceiver Clock Generation ..42 USB-to-UART Bridge HDMI Video Output LCD Character Display(16 x 2) ,,,,,,,,,,47 I2C Bus 48 Status lEds 50 User I/O Switches VITa 57. 1 FMCl HPC Connector(Partially populated) 58 VITA 57.1 FMC2 HPC Connector(Partially Popu lated) 58 Power management XADC Analog-to-Digital Converter Configuration Options 77 Appendix A: Default Switch and Jumper Settings GPIO DIP Switch sw2 Configuration DIP Switch SW11............. 80 Default Jumper Settings Appendix B: VITA 57.1 FMC Connector Pinouts Appendix C: Master Constraints File Listing VC707 Board XDC Listing 85 VC707 Evaluation board www.xilinx.com Send feedback UG885(v17.1) August12,2016 &A XILINX Appendix D: Board Setup Installing VC707 Board in a PC Chassis Appendix E: Board Specifications Dimensions 111 Environmental 番·番 111 Temperature 111 humidity ,,,,,,,,,111 Operating Voltage Appendix F: Additional Resources Xilinx Resources 113 Solution centers References 113 Appendix G: Regulatory and Compliance Information Declaration of Conformity .........115 Directives Standards .115 Electromagnetic Compatibility 115 Safety ......115 Markings Send feedback www.xilinx.com VC707 Evaluation board UG885(V1.7.1) August12,2016 R XILINX Chapter 1 VC707 Evaluation board features Overview The vc707 evaluation board for the virtexB-7 FPGa provides a hardware environment for developing and evaluating designs targeting the Virtex-7 XC7VX485T-2FFG176IC FPGA The vC707 board provides features common to many embedded processing systems, including a DDR3 SODIMM memory, an 8-lane PCI Express@ interface, a tri-mode Ethernet PHY, general purpose I/O, and two UART interfaces. Other features can be added by using mezzanine cards attached to either of two VITA-57 FPGA mezzanine connectors(FMC) provided on the board. Two high pin count(HPC) FMCs are provided Sce vc707 Board Features for a complete list of fcatures. The details for cach feature arc described in Feature Descriptions, page 10 Additional Information bee Appendix F, Additional Resources for references to documents, files and resources relevant to the vc707 board VC707 Board Features Virtex-7 XC7VX485T-2FFG1761C FPGA I GB DdR3 memory SODIMM 128 MB Linear byte peripheral interface(BPn)Flash memory USB 2.0 ULPI Transceiver ecure Digital(SD) connector USB TAG through Digilent module Clock generation Fixed 200 MHz LVds oscillator(differential) I-C programmable LVdS oscillator(differential) SMA connectors(differential) SMA connectors for GTX transceiver clocking GTX transceivers FMCI HPC connector(eight gtX transceivers) FMC2 HPC connector (eight GTX transceiver) SMA connectors (one pair each for TX, RX, and reFCLK) PCI Express (eight lanes Small form-factor pluggable plus(SFP+)connector VC707 Evaluation board www.xilinx.com Send feedback UG885(v17.1) August12,2016 Chapter 1: VC707 Evaluation Board Features &A XILINX Ethernet PhY SGMII interface(rJ-45 connector) PCI Express endpoint connectivity Genl 8-lane(x8) Gen2 8-lane(x8) SFP+ Connector 10/ 100/1000 tri-speed Ethernet PhY USB-to-UART bridge HDMITM codec ·1Cbus I2C MUX IC EEPROM (1KB) USER IC programmable LVDS oscillator DDR3 SODIMM Socket HdMI codec FMCI HPC connector FMC2 HPC connector SFP+ connector 1-C programmable jitter-attenuating precision clock multiplier Status leds Ethernet status · Power good FPGA INIT TPGA DONE User I/C User LEDs(eight GPIO) User pushbuttons(five directional) CPU reset pushbutton User DIP switch( 8-pole GPIO) User SMA GPIO connectors(one pair) LCD character display(16 characters x 2 lines Switches Power on/off slide switch FPGA_PROB_B pushbutton Configuration mode dip switch VITA 57.1 FMC1 HPC Connector VITA 57.1 FMC2 HPC Connector Power management PMBus voltage and current monitoring through Ti power controller XADC heade Configuration options Send feedback www.xilinx.com VC707 Evaluation board UG885(V1.7.1) August12,2016 &A XILINX Overview Linear BPI Flash memory USB JTAG configuration port Platform cable header JTAG configuration port The VC707 board block diagram is shown in Figure 1-1. The vC707 board schematic available for download from the VC707 Evaluation Kit product page on the docs s are Designstabatwww.xilinx.com/vc707 Caution! The VC707 board can be damaged by electrostatic discharge(ESD). Follow standard Esd prevention measures when handling the board 1 GB DDR3 Memory FMC Connectors 10/100/1000 Ethernet (SODIMM) (HPC/HPC) Interface Differential clock 128 MB Linear bPl GTX SMA Clock Flash memory XADC Header USB 2.0 ULPI PHY Virtex-7 FPGA XC7VX485T-2FFG1761C User Switches 8-lane PCI Express Buttons, and LEDs Edge Connector HDMI Vide LCD Display Interface (2 line x 16 characters 1 KB EEPROM(12c) DIP Switch SW11 JTAG Interface 12c Bus Switch Config and flash Addr USB-to-UART Bridge mini-B USB Connector SFP+ single Cage UG885c101030512 Figure 1-1: vC707 Board Block Diagram VC707 Evaluation board www.xilinx.com Send feedback UG885(v17.1) August12,2016 Chapter 1: VC707 Evaluation Board Features &A XILINX Feature Descriptions Figure 1-2 shows the VC707 board Each numbered feature that is referenced in Figure 1-2 described in the sections that follow Note: The image in Figure 1-2 is for reference only and might not reflect the current revision of the board Round callout references a component L on the back side of the boar compo Square callout references a component on the front side of the board 删 ⅫLNX湖F VIRTE User rotary switch located under lcD Figure 1-2: VC707 Board Component Locations Table 1-1: VC707 Board Component Descriptions Schematic Reference Component Description 0381418 Callout Notes Designator Page Number U1 Virtex-7 FPGa with cooling fan XC丌X485T2FFG1761C DDR3 SODIMM memory (1 GB) Micron mtSJTF12864HZ-1G6G1 21 BPI parallel NOR flash memory(1 Gb) Micron pc28FO0AG18FE U8,J2 USB ULPI transceiver, USB mini-B connector SMSC USB3320-EZK U29 SD card interface connector Molex67840-8001 USB JTAG interface, USB micro-B connect agilent USB JTAG module U51 System clock, 200 MHz, LVDS (back sidc of board) SiTimc si9102243、25E200.0000 10 Send feedback www.xilinx.com VC707 Evaluation board UG885(V1.7.1) August12,2016

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