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JTAG interface signals
The following table describes the signals on the JTAG interfaces:
Table1.JTAG signals
Signal I/O Description
DBGAC
K
-
This pin is connected in the RVI run control unit, but is not
supported in the current release of the software. It is reserved for
compatibility with other equipment to be used as a debug
acknowledge signal from the target system. It is recommended
that this signal is pulled LOW on the target.
DBGRQ -
This pin is connected in the RVI run control unit, but is not
supported in the current release of the software. It is reserved for
compatibility with other equipment to be used as a debug request
signal to the target system. The RVI software maintains this signal
as LOW.
When applicable,RVI uses the scan chain 2 of the processor to put
the processor in debug state. It is recommended that this signal is
pulled LOW on the target.
GND - Ground.
nSRST
Input/
output
Active Low output from RVI to the target system reset, with a
4.7kΩ pull-up resistor for de-asserted state. This is also an input to
RVI so that a reset initiated on the target can be reported to the
debugger.
This pin must be pulled HIGH on the target to avoid unintentional
resets when there is no connection.
nTRST Output
Active Low output from RVI to the Reset signal on the target JTAG
port, driven to the VTref voltage for de-asserted state. This pin
must be pulled HIGH on the target to avoid unintentional resets
when there is no connection.
RTCK Input Return Test Clock signal from the target JTAG port to RVI. Some