PYNQ-Z2 HDMI DEMO

*************************************************************************************** * PROJECT ARCHIVE SUMMARY REPORT * * (archive_project_summary.txt) * * PLEASE READ THIS REPORT TO GET THE DETAILED INFORMATION ABOUT THE PROJECT DATA THAT * WAS ARCHIVED FOR THE CURRENT PROJECT * * The report is divided into following five sections:- * * Section (1) - PROJECT INFORMATION * This section provides the details of the current project that was archived * * Section (2) - INCLUDED/EXCLUDED RUNS * This section summarizes the list of design runs for which the results were included * or excluded from the archive * * Section (3) - ARCHIVED SOURCES * This section summarizes the list of files that were added to the archive * * Section (3.1) - INCLUDE FILES * This section summarizes the list of 'include' files that were added to the archive * * Section (3.1.1) - INCLUDE_DIRS SETTINGS * This section summarizes the 'verilog include directory' path settings, if any * * Section (3.2) - REMOTE SOURCES * This section summarizes the list of referenced 'remote' files that were 'imported' * into the archived project * * Section (3.3) - SOURCES SUMMARY * This section summarizes the list of all the files present in the archive * * Section (3.4) - REMOTE IP DEFINITIONS * This section summarizes the list of all the remote IP's present in the archive * * Section (4) - JOURNAL/LOG FILES * This section summarizes the list of journal/log files that were added to the archive * * Section (5) - CONFIGURATION SETTINGS/FILES * This section summarizes the configuration settings/files that were added to the archive * *************************************************************************************** Section (1) - PROJECT INFORMATION --------------------------------- Name = hdmi-out Directory = D:/WORK/FPGA/Pynq-hdmi-out/proj WARNING: Please verify the compiled library directory path for the following property in the current project. The path may point to an invalid location after opening this project. This could happen if the project was unarchived in a location where this path is not accessible. To resolve this issue, please set this property with the desired path before launching simulation:- Property = compxlib.xsim_compiled_library_dir Path = Section (2) - INCLUDED RUNS --------------------------- The run results were included for the following runs in the archived project:- <synth_1> <hdmi_out_axi_dynclk_0_0_synth_1> <hdmi_out_axi_gpio_btn_0_synth_1> <hdmi_out_axi_gpio_hdmi_0_synth_1> <hdmi_out_axi_gpio_led_0_synth_1> <hdmi_out_axi_gpio_sw_0_synth_1> <hdmi_out_axi_vdma_0_0_synth_1> <hdmi_out_axis_subset_converter_0_0_synth_1> <hdmi_out_proc_sys_reset_0_0_synth_1> <hdmi_out_proc_sys_reset_1_0_synth_1> <hdmi_out_processing_system7_0_0_synth_1> <hdmi_out_rgb2dvi_0_0_synth_1> <hdmi_out_v_axi4s_vid_out_0_0_synth_1> <hdmi_out_v_tc_0_0_synth_1> <hdmi_out_xlconcat_0_0_synth_1> <hdmi_out_xlconstant_0_0_synth_1> <hdmi_out_xlconstant_1_0_synth_1> <hdmi_out_xbar_0_synth_1> <impl_1> Section (3) - ARCHIVED SOURCES ------------------------------ The following sub-sections describes the list of sources that were archived for the current project:- Section (3.1) - INCLUDE FILES ----------------------------- List of referenced 'RTL Include' files that were 'imported' into the archived project:- None Section (3.1.1) - INCLUDE_DIRS SETTINGS --------------------------------------- List of the "INCLUDE_DIRS" fileset property settings that may or may not be applicable in the archived project, since most the 'RTL Include' files referenced in the original project were 'imported' into the archived project. <sources_1> fileset RTL include directory paths (INCLUDE_DIRS):- None <sim_1> fileset RTL include directory paths (INCLUDE_DIRS):- None Section (3.2) - REMOTE SOURCES ------------------------------ List of referenced 'remote' design files that were 'imported' into the archived project:- <hdmi_out_axi_dynclk_0_0> d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/9097/src/mmcme2_drp.v d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/9097/src/axi_dynclk_S00_AXI.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/9097/src/axi_dynclk.vhd <hdmi_out_axi_gpio_btn_0> d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/52cb/hdl/lib_cdc_v1_0_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/e956/hdl/interrupt_control_v3_1_vh_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/cb07/hdl/axi_gpio_v2_0_vh_rfs.vhd <hdmi_out_axi_gpio_hdmi_0> d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/52cb/hdl/lib_cdc_v1_0_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/e956/hdl/interrupt_control_v3_1_vh_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/cb07/hdl/axi_gpio_v2_0_vh_rfs.vhd <hdmi_out_axi_gpio_led_0> d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/52cb/hdl/lib_cdc_v1_0_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/e956/hdl/interrupt_control_v3_1_vh_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/cb07/hdl/axi_gpio_v2_0_vh_rfs.vhd <hdmi_out_axi_gpio_sw_0> d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/52cb/hdl/lib_cdc_v1_0_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/e956/hdl/interrupt_control_v3_1_vh_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/cb07/hdl/axi_gpio_v2_0_vh_rfs.vhd <hdmi_out_axi_vdma_0_0> d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/52cb/hdl/lib_cdc_v1_0_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/832a/hdl/lib_pkg_v1_0_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/ebc2/simulation/fifo_generator_vlog_beh.v d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/ebc2/hdl/fifo_generator_v13_1_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/ebc2/hdl/fifo_generator_v13_1_rfs.v d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/c387/hdl/lib_fifo_v1_0_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/4158/simulation/blk_mem_gen_v8_3.v d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/0dfc/hdl/lib_bmg_v1_0_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/6039/hdl/lib_srl_fifo_v1_0_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/43a6/hdl/axi_datamover_v5_1_vh_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/450f/hdl/axi_vdma_v6_3_1.vh d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/450f/hdl/axi_vdma_v6_3_rfs.v d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/450f/hdl/axi_vdma_v6_3_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/4158/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/ebc2/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd <hdmi_out_axis_subset_converter_0_0> d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/acf8/hdl/axis_infrastructure_v1_1_0.vh d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/acf8/hdl/axis_infrastructure_v1_1_vl_rfs.v d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/341f/hdl/axis_register_slice_v1_1_vl_rfs.v d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/bd78/hdl/axis_subset_converter_v1_1_vl_rfs.v <hdmi_out_proc_sys_reset_0_0> d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/52cb/hdl/lib_cdc_v1_0_rfs.vhd d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/5db7/hdl/proc_sys_reset_v5_0_vh_rfs.vhd <hdmi_out_proc_sys_reset_1_0> d:/WORK/FPGA/Pynq-hdmi-out/src/bd/hdmi_out/ipshared/52