MT29F32G08CBABA.pdf

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MT29F32G08CBABA.pdf
Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Contents General Description .··:······ Asynchronous and Synchronous Signal Descriptions Signal Assignments…… Package Dimensions 14 Architecture…, 19 Device and array organization ... 着鲁垂 20 Bus operation- Asynchronous Interface…… 27 Asynchronous Enable/ Standby…………,…,…,…,…,…,…,…,…,…,…,…,…,…,……,27 Asynchronous Bus Idle 看看,D,垂 27 Asynchronous Commands 28 Asynchronous addresses 29 Asynchronous Data Input….….........….....,..,30 Asynchronous Data output 31 Write protect .. Ready busy# 32 Bus Operation -Synchronous Interface..... 37 Synchronous enable/ Standby...….…. ·: :.··.··· 38 Synchronous bus idle/ driving 番 ,38 Synchronous commands∴.…11.39 Synchronous addresses 40 ynchronous DDR Data Input.….…,…,…,…,…,… 41 Synchronous DDR Data Output 42 Write protect 44 Ready/Busy# 44 Device initialization. Activating Interfaces.… 46 Activating the asynchronous Interface 16 Activating the Synchronous Interface………… 46 Command definitions 48 Reset Operations… 50 RESET(FFh)........................ 50 SYNCHRONOUS RESET (FCh) ···.·:····..:.· 51 Identification Operations......................... 52 READ ID(90h) 52 READ ID Parameter tables ·.::.·· 53 Configuration Operations .54 SET FEATURES (EFh).............. 54 GET FEATURES(ELh)…… 55 READ PARAMETER PAGE (ECh) 59 Parameter Page Data Structure Tables…………… 60 READ UNIQUE ID(EDh)…,,…,…,…,…,…,… 71 Status Operations.,,,,,,,,,…,…………,… ..·.··; 7 READ STATUS (7Oh) ·····:· ················.···..······· READ STATUS ENHANCED(78h)..................... 74 Column Address Operations 5 CHANGE READ COLUMN (05h-EOh) 75 CHANGE READ COLUMN ENHANCED(06h-EOh 76 CHANGE WRITE COLUMN 77 CHANGE ROW ADDRESS (8.5h 78 Read operations :···.········;······;·········· 80 icon Technology, Inc. reserves the right to change products or specifications without notice Rev f12/09 EN e 2008 Micron Te ogy, Inc Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND READ MODE(00h)∴,282 READ PAGE(O0h-30h)…. ,83 READ PAGE CACHE SEQUENTIAL (31h).................. 84 READ PAGE CACHE RANDOM (OOh-3lh) 85 READ PAGE CACHE LAST (3Fh .:······:·.··:·.···· 87 READ PAGE MULTI-PLANE (00h-32h) 88 Program Operations…………,…,…… PROGRAM PAGE(80h-10h)... 看4音;垂垂 ,90 PROGRAM PAGE CACHE (80h-15h) 92 PROGRAM PAGE MULTI-PLANE 80h-1lh 94 Erase Operations……,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,……,…,……,…,96 ERASE BLOCK(60h-Doh)………………………… ∴96 ERASE BLOCK MUITI-PLANE (60h-D1h) .97 Copyback Operations……………….… 翻垂着,。 98 COPYBACK READ(00h-35h)…………… 99 COPYBACK PROGRAM (85h-10h 100 COPYBACK READ MULTI-PLANE (00h-32h) 100 COPYBACK PROGRAM MULTI-PLANE(85h-llh) 101 One- Time Programmable(OTP) Operations……,,…,,…,,… 着看·垂 102 PROGRAM OTP PAGE(80h-10h)......... l03 PROTECT OTP AREA(80h-loh)…,……,104 READ OTP PAGE (00h-30h …105 Multi-Plane operations l06 Multi- Plane addressing………………,106 Interleaved Die(Multi-LUN Operations........,......... l07 Error management 108 Output Drive Impedance 看.. n109 AC Overshoot/Undershoot Specifications 112 Synchronous Input Slew Rate l13 Output Slew rate ..··········· 14 Electrical Specifications ·.:::.::··:· l15 Electrical Specifications-DC Characteristics and Operating Conditions(Asynchronous) l17 Electrical Specifications-DC Characteristics and Operating Conditions(Synchronous).........1 18 E! lectrical Specifications- DC Characteristics and Operating Conditions (Vcco)…………………118 Electrical Specifications-AC〔 haracteristics and Operating Conditions( Asynchronous).……,…,…,,,19 Electrical Specifications- AC Characteristics and Operating Conditions(Synchronous 121 Electrical Specifications- Array Characteristics 124 Asynchronous Interface Timing diagrams…… 125 Synchronous interface Timing Diagrams..…..….… ····t 136 Revision History…………… ∴158 ReV. F, Production-12/ 09 158 Rev.E-8/09. 158 Rev.D-2/09 158 Rev.C-1/09 158 Rev.B-12/08 垂垂非;垂非看音D看 159 Rev.A-11/08 l60 icon Technology, Inc. reserves the right to change products or specifications without notice Rev f12/09 EN e 2008 Micron Te ogy, Inc Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND List of tables Table1: Asynchronous and Synchronous Signal definitions∴…… 9 Table2: Array Addressing for Logical Unit(LUN)……,…,…,…,…,…,,…,……,……………,26 Table 3: Asynchronous Interface Mode selection 27 Table4: Synchronous Interface Mode selection………… ∴37 Table 5: Command set 48 Table 6: Read id parameters for address ooh 着鲁垂 53 Table 7: Read id Parameters for Address 20h 53 Table8;: Feature Address Definitions∴….54 Table9: Feature Address olh: Timing mode∴…,…,,,,…,…,,,,, 56 Table 10: Feature Addresses 1Oh and 80h: Programmable Output Drive Strength 56 Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength 57 Table12; Feature Addresses9oh: Array Operation Mode.…,…,…,,…,…,…,…,,,……,57 Table 13: Parameter Page Data Structure 60 Table 14: Status Register Definition…,…,……,…,,,……,72 Table15:otpareadetails4.www.w..wwnwwwnnnwwwnnnwwwwwwwwwwwww103 Table 16: Error Management Details l08 Table 17: Output Drive Strength Test Conditions(ccQ=1.7-195V)…………………………………109 Table 18: Output Drive Strength Impedance Values(VccQ-1.7-1.95V) ,109 Table 19: Output Drive Strength Conditions(Vcco=2.7-3.6V) Table 20: Output Drive Strength Impedance Values (VCCQ=2.7-3.6v) 110 l10 Table21:Pul- Up and Pull-Down Output Impedance Mismatch……,…,…,…,…,…,…,…,…,…,11l Table 22: Overshoot/Undershoot parameters 112 Table 23: Test Conditions for Input Slew Rate Table24: Input Slew Rate(cco=1.7-1.95V)…… 113 Table25: Input Slew Rate(VccQ=27-3.6V)…………………… ..:· l13 Table 26: Test Conditions for Output slew rate 114 Table27: Output Slew Rate(vcco=1.7-1.95V)………………………………… Table28: Output Slew Rate(Vcco=27-3.6V)……,…,…,…,…,,…,…,…,……………14 Table 29: Absolute Maximum Ratings by Device..... 115 Table 30: Recommended Operating Conditions Tablo31: Valid Blocks per LUN…….…..…….…….…,…, l15 Table32: Capacitance:100- Ball BGa Package,……,…, 116 Table 33: Capacitance: 48-Pin TSOP Package ·· l16 Table34: Capacitance:52- Pad LGa Package…………,…,…,…,…,…,…,……,116 Table 35: Test Conditions 117 Table 36: DC Characteristics and Operating Conditions(asynchronous Interface) ..117 Table 37: DC Characteristics and Operating Conditions(Synchronous Interface) Table38: DC Characteristics and Operating Conditions(3.3 VACCo)……,…,…,…,…,……,118 Table39:DC( haracteristics and Operating Conditions(1.8 VVccQ)…………… l19 Table 40: AC Characteristics: Asynchronous Command, Address, and Data Table4l: AC Characteristics: Synchronous Command, Address, and data..…………,…,…,…………12l Table42: Array Characteristics……,…,…,…,…,,…,…,,…,,…,,,,………,124 icon Technology, Inc. reserves the right to change products or specifications without notice Rev f12/09 EN e 2008 Micron Te ogy, Inc Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND List of Figures Figure 1: Part Numbering .··:······ 2 Figure 2: 48-Pin TSOP Type l (Top View) 非看音看·垂 Figure3:52- Pad lga( Top view)∴…… Figure 4: 100-Ball BGA (Ball-Down, Top view) Figure 5: 48-Pin TSOP-Type 1 CPL(Package Code: WP) 14 Figure 6: 52-Pad vega Figure 7: 100-Ball VBGA-12mm x 18mm(Package Code: HI 16 Figure8:100- Ball tbga-12mmx18mm( Package Code:H2)……,…,…,…,,…,…,…,………,17 Figure 9: 100-Ball LBGA-12mm x 18mm(Package Code: H3 18 Figure 10: NAND Flash Die (LUN) Functional Block Diagram 19 Figure 11: Device Organization for Single-Die Package (TSOP/BGA) 20 Figure12: Device Organization for Two- Die Package(TSOP).…,…,…,…,…,…,,…,………20 Figure 13: Device Organization for Two-Die Package (BGA/LGA) 21 Figure 14: Device Organization for Four- Die Package(ISOP)….………,…,,,……,22 igure 15: Device Organization for Four-Die Package with CE# and CE2#(BGA/LGa) 23 Figure 16: Device Organization for Four-Die Package with CE#, CE2#, CE3#, and CE4#(BGA/LGA) .24 Figure 17: Device Organization for Eight-Die Package(BGA/LGA) :.··.··· 25 Figure18: Array Organization per Logical Unit(LUN)…………,…… 26 Figure19: Asynchronous Command Latch Cycle………,…,…,…,…,…,,…,…,…,…,,…,…,28 Figure 20: Asynchronous Address latch Cycle 29 Figurc21: Asynchronous Data Input Cycles…………,…,…,…,…,…,…,,…,…,…,…,30 Figure22: Asynchronous Data Output Cycles……,…,…,…,, 31 Figure 23: Asynchronous data Output cycles(edo mode) 32 Figure24:READ/BUSY# Open drain…………… ·非垂 33 Figure 25: Fall and 'Rise(Vcco=2.7-3.6V) 34 Figure26: Fall and rise(vco=1.7-195V…… ······,· 34 Figure27: IOL VS Rp(VcQ=273.6V)………………………………………………………………35 Figure28: IOL VS Rp(Vco=1.7-1.95V)…… 35 Figure29: TC vS Rp…,…,, 36 Figure30: Synchronous Bus Idle/ Driving behavior……… 39 Figure3l: Synchronous Command cycle.…………,…,…,…,…,…,…,…,…,…,…,…,…,…,…,……,40 Figure 32: Synchronous Address Cycle ··::·..···· 41 Figure 33: Synchronous DDR Data Input Cycles...... 42 Figure34: Synchronous DDR Data Output Cycles…………………,…,…,…,,…,…,…,… 44 Figure35:R/B# Power- On behavior,,…,,… 45 Figure 36: Activating the Synchronous Interface 47 Figure37: RESET(Frh) Operation……… 50 Figure 38: SYNCHRONOUS RESET Figure 39: READ ID (90h)with 00h Address Operation 52 figure40: READ ID(9oh)with20 h Address operation…………… 52 Figure41: SET FEATURES(EFh) Operation………,… 55 Figure42: GET FEATURES(EEh) Operation…,…,…,…,…,…,…,…,…………55 Figure 43: READ PARAMETER(ECh)Operation 59 Figure44: READ UNIQUE ID( EDh)Operation………,…,…,…,…,…,…,…,,…,……,…….…,…,71 Figure45: READ STATUS(7oh) Operation…,…,,…,……,…,…,…,…,,…,…,…,74 Figure 46: READ STATUS ENHANCED(78h)Operation 74 Figure47: CHANGE READ COLUMN(5h-EOh) Operation…………… Figure48: CHANGE READ COLUMN ENHANCED(06h-EOh) Operation……,…,…,, 76 Figure 49: CHANGE WRITE COLUMN (85h) Operation 77 Figure50: CHANGE ROW ADDRESS(85h) Operation………,……………,79 icon Technology, Inc. reserves the right to change products or specifications without notice Rev f12/09 EN e 2008 Micron Te ogy, Inc Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Figure 52: READ PAGE CACHE SEQUENTIAL (3 lh) operation Figure51: READ PAGE(00h-30h) Operation…………… 83 84 Figure53: READ PAGE CACHE RANDOM(ooh-3lh) Operation………,…,…,……,… 86 Figure 54: READ PAGE CACHE LAST (3Fh)Operation 87 Figure55: READ PAGE MULTI- PLANE(00h-32h) Operation……,…,,…,,…,,,89 Figure 56: PROGRAM PAGE(80h-10h)Operation 91 Figure57: PROGRAM PAGE CACHE(80h-15h) Operation( Start)……………………… 93 Figurc58: PROGRAM PAGE CACHE(80h-15h) Opcration(End)…………… 93 Figure59: PROGRAM PAGE MULTI- PLANE(80h-1lh) Operation.…,…,…,,…,…,95 Figure60: ERASE BLOCK(60h- DOh)Operation…………………….…….….……,96 Figure61: ERASE BLOCK MULTI- PLANE(60h-Dih) Operation∴……………,…,…,…,,…,,……,,97 Figure 62: COPYBACK READ (00h-35h)Operation................... ∴99 Figure 63: COPYBACK READ(0Oh-35h)with CHANGE READ COLUMN (O5h-FOh)Operation .99 Figure64: COPYBACK PROGRAM(⑧85h-l0h) Operation………………………… 100 Figure 65: COPYBACK PROGRAM (85h-10h)with CHANGE WRITE COLUMn(85h)Operation....... 100 Figure 66: COPYBACK PROGRAM MULTI-PLANE (85h-llh) Operation .101 Figurc 68: PROGRAM OTP PAGE (80h- 10h)with CHANGE WRITE COLUMN(85h) opcration Figure67: PROGRAM OTP PAGE(80h-l0h) Operation…………,……,…………,103 104 Figure 69: PROTECT OTP AREA(80h-10h)Operation l05 Figure 70: READ OTP PAGE(00h-30h)Operation l05 Figure7l: Overshoot……,…,…,…,… 看。垂 112 Figure72; Undershoot……,…,…,…,…,…,…,…,…,…,…,…,…,……………,112 Figure 73: RESET Operation l25 Figure 74: READ STATUS Cycle 125 Figure 75 READ STATUS ENHIANCED Cycle 翻看垂 ··· 126 Figure 76: READ PARAMETER PAGE ..127 Figure77: READ PAGE……………… .·.·· ∴127 Figure 78: READ PAGE Operation with CEt"Dont Care 128 Figure79: CHANGE READ COLUMN∴… 129 Figure80: READ PAGE CACHE SEQUENTIAL∴…… 130 Figure8l: READ PAGE CACHE RANDOM……………… ,131 Figure82: READ ID Operation…… :·····::···· 132 Figure 83: PROGRAM PAGE Operation Figure 84: PROGRAM PAGE Operation with CE#"Dont care l32 ..·:········.·,·:·········· 133 Figure 85: PROGRAM PAGE Operation with CHANGE WRITE COLUMN 133 Figure 86: PROGRAM PAGE CACHE 134 Figure 87: PROGRAM PAGE CACHE Ending on 15h 134 Figure88: COPYBACK… l35 Figure 89: ERASE BLOCK Operation ····t ∴135 Figure 90: SET FEATURES Operation ∴136 Figurc 91: READ ID Opcration 137 Figure 92: GET FEATURES Operation 138 Figure 93: RESET (FCh)Operation ∴139 Figure94: READ STATUS Cycle…………… 140 Figure 95: READ STATUS ENHANCED Operation l41 Figure 96: READ PARAMETER PAGE Operation .142 Figure97: READ PAGE Operation………,…,…,…,……,…,……,…,…,…,…,…,……,143 Figure98: CHANGE READ COLUMN…..,………………,,,,,,,,…………144 Figure 99: READ PAGE CACHE SEQUENTIAL(1 of 2 145 Figure 100: READ PAGE CACHE SEQUENTIAL (2 of 2) 垂垂 l46 Figurc101: READ PAGE CACHE RANDOM(lof2)……,…,,…,,…,…, 147 Figure 102: READ PAGE CACHE RANDOM (2 of2 147 icon Technology, Inc. reserves the right to change products or specifications without notice Rev f12/09 EN e 2008 Micron Te ogy, Inc Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Figure103: Multi- Plane Read Page(lof2),…,…,…,…,……,…… 148 Figure104; Multi- Plane Read Page(2of2)……,…,…,…,… 149 Figure 105: PROGRAM PAGE Operation (l of2).............. 150 Figure 106: PROGRAM PAGE Operation(2of2)………… 150 Figure 107: CHANGE WRITE COLUMN.. .:······:·.··:·.···· 151 Figure108:Muli- Plane Program Page……,…,…,…,…,…,,…,…,……,152 figure109: ERASE BLOCK………… ∴153 Figurc 110: COPYBACK(l of 3) 看4音;垂垂 153 Figure11l: COPYBACK(2of3),,…,,…,…,,… 154 Figure1l2: COPYBACK(3of3)….……. 154 Figure113: READ OTP PAGE….……,…,…,…,…,…,…,…,…,…,…,…,…,…,…………155 Figure 114: PROGRAM OTP PaGe (1 of 2) ∴156 Figure 115: PROGRAM OTP PAGE (2 of 2) 156 Figure 116: PROTECT OTP AREA 157 icon Technology, Inc. reserves the right to change products or specifications without notice Rev f12/09 EN e 2008 Micron Te ogy, Inc Micron Confidential and Proprietary Micron 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND General Description General Description Micron NANd Flash devices include an asynchronous data interface for high-perform ance I/O operations. These devices use a highly multiplexed 8-bit bus(DQx)to transfer commands,address, and data. There are five control signals used to implement the asyn chronous data interfacc: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection(WP#) and monitor device status(R/B#) This micron nand flash device additionally includes a synchronous data interface for high-performance I/O operations. When the synchronous interface is active, WE# be comes clK and re# becomes w/r# data transfers include a bidirectional data strobe ( DQS This hardware interface creates a low pin-count device with a standard pinout that re mains the same from one density to another, enabling future upgrades to higher densi ties with no board redesign. a target is the unit of memory accessed by a chip enable signal. a target contains one or more nand Flash die. a NANd Flash die is the minimum unit that can independently execute commands and report status. A nand Flash die, in the onfi specification, is referred to as a logical unit (LUN. For further details, see Device and Array organization. Asynchronous and Synchronous Signal Descriptions Table 1: Asynchronous and Synchronous Signal Definitions Asynchronous Synchronous Signal? Signal Type Description2 AlE ALE Input Address latch enable: Loads an address from Dox into the address reg ister CE# CE# Input Chip enable: Enables or disables one or more die(LUNs)in a target CLE CLE put Command latch enable: Loads a command from DQx into the com mand register. DOX DOX vO Data inputs/outputs: The bidirectional l/Os transfer address, data, and command information DQS Data strobe: Provides a synchronous reference for data input and out RE# W/R# Input Read enable and write/read: RE# transfers serial data from the nand Flash to the host system when the asynchronous interface is active When the synchronous interface is active, W/R# controls the direction of DQx and dQs WE# CLK Input Write enable and clock: WE# transfers commands, addresses, and seri al data from the host system to the Nand Flash when the asynchronous interface is active. When the synchronous interface is active, CLK latches command and address cycle WP# WP# Input Write protect: Enables or disables array PROGRAM and ERASE opera tions R/B# R/B# Output Ready/busy: An open-drain, active-low output that requires an exter- nal pull-up resistor. This signal indicates target array activity Supply Vcc: Core power supply icon Technology, Inc. reserves the right to change products or specifications without notice Rev f12/09 EN Micron Confidential and Proprietary Micron 32G, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous and Synchronous signal Descriptions Table 1: Asynchronous and Synchronous Signal Definitions ( Continued) Asynchronous Synchronous Signal Signal Type Description2 CCQ V CCQ SupplyVcco: l/0 power supply SS SupplyVss: Core ground connection Supply VssQ: vO ground connection NO NO No connect: NCs are not internally connected. they can be driven or left unconnected DNU DNU Do not use: DNUs must be left unconnected RFU Reserved for future use: RFUs must be left unconnected Notes: 1. See Device and Array Organization for detailed signal connections 2. See Bus Operation -Asynchronous Interface (page 27)and Bus Operati nous Interface (page 37) for detailed asynchronous and synchronous interface signa descriptions icon Technology, Inc. reserves the right to change products or specifications without notice Rev f12/09 EN 10

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chuanyu0208 太尼玛贵了,买不起啊
2019-11-08
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marioshuairen 确实有点贵,但是需要没办法了
2013-08-05
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mingyunzzu 资料是不错,就是太贵了点吧!
2013-05-31
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