AWR1243 Cascade.pdf
需积分: 5 89 浏览量
2020-05-31
21:52:14
上传
评论 1
收藏 242KB PDF 举报
1
SWRA574A–October 2017–Revised December 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
AWR1243 Cascade
Application Report
SWRA574A–October 2017–Revised December 2017
AWR1243 Cascade
Anil Kumar K V, Sreekiran, Samala, Karthik Subburaj, Chethan Kumar Y.B.
ABSTRACT
This application report describes TI’s cascaded mmWave radar system. This solution is based on TI’s
AWR1243 radar chip. Several of these chips are cascaded and operated in synchronism. Each AWR1243
chip supports up to four receive and three transmit antennas. Cascading multiple such chips allows the
radar system to operate with more receive and transmit antennas, thereby improving target detection and
resolution in comparison with a single AWR1243 radar chip based system. Cascading of two and four
AWR1243 chips is illustrated in this application note, targeting automotive applications such as Adaptive
Cruise Control, Collision Warning, Emergency Braking, and Semi and Fully Autonomous Driving.
Contents
1 Cascaded AWR1243 System ............................................................................................. 2
2 Synchronization of AWR1243 Chips ...................................................................................... 4
3 Connectivity................................................................................................................... 8
4 20 GHz LO Sync Link Budget.............................................................................................. 9
5 Software Messaging ....................................................................................................... 10
6 Advantages of AWR1243 Cascading System ......................................................................... 13
7 References .................................................................................................................. 13
List of Figures
1 A Two Chip Cascade System.............................................................................................. 2
2 A Four Chip Cascade System ............................................................................................. 3
3 20 GHz Mux Options in the Chip .......................................................................................... 4
4 Example of LO Distribution in 2-Chip Star Topology.................................................................... 5
5 Frame (Burst) Timing and Clock Generation in AWR1243............................................................. 6
6 Frame (Burst) Timing Generation in Two Chip Cascade Example ................................................... 7
7 20 GHz LO - Link Budget................................................................................................... 9
List of Tables
1 DIG_SYNC_IN Imbalance Summary...................................................................................... 8
2 Recommended Combinations of Pins to be Used in 20 GHz LO ..................................................... 8
3 Channel Configuration Message ......................................................................................... 11
4 Profile Configuration Message ........................................................................................... 11
5 Chirp Configuration Message............................................................................................. 12
6 Frame Configuration Message ........................................................................................... 12
剩余14页未读，继续阅读
资源评论
