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Spartan-3AN FPGA In-System Flash User Guide
Table of Contents Chapter 1: Overview and SPL_ACCESS Interface In-System Flash Summary Accessing In-System Flash Memory After Configuration SPI_ACCESS Design Primitive HDL Instantiation Examples ··· 10 ⅤHDL.,,,,,,,,,,,,,,,,,, ,,,,,,,,,,10 Verilog SPI Transactions Example Detailed Command Sequence ,12 Simulation Support .13 Related materials and References ,,,,,,,,,14 Chapter 2: In-System Flash Memory Architecture Block Diagram Flash Memory array 15 Addressing Overview Addressing Modes 垂垂垂 Default Addressing mode .....19 Delivered State ...20 Memory allocation Tables 20 MultiBoot Configuration Bitstream Guidelines 26 Align to Flash Sector boundaries 26 Additional Memory Space Required for DCM_WAIT 26 User Data Storage Guidelines Chapter 3: Read Commands Fast read .30 Random read Page to Buffer Transfer 33 Buffer read Chapter 4: Write and Program Commands Buffer write Buffer to Page Program with Built-in Erase Buffer to Page Program without Built-in Erase Page Program Through Buffer Page to Buffer Compare(Program Verify) 46 Pre-initializing SRAM Page Buffer Contents 47 EEPROM-Like, Byte-Level Write Operations Sequential vs Random Page Programming, Cumulative Operations 48 .48 Spartan -3AN In-System Flash User Guide Www.xuinX.com UG333(21) January15,2009 XL|NX° Auto Page rewrite Chapter 5: Erase Commands Sector Protect and sector lockdown Prevent erase operations .51 Erased state Page erase 52 Block erase 54 Sector erase ..57 Sector Addressing∴ 音番 58 Default Addressing Mode. 58 Operation Timing Chapter 6: Status and Information Commands Status Register ..63 READY/BUSY Compare ISF Memory Size∴ Sector Pl 666 555 g 66 Status Register Read ,,,,,,66 Information read ··: Manufacturer identifier 68 Family code/ Memory density Code Memory Type/Product Version Code Extended Device information Field ....69 Chapter 7: Power Management Active Mode 71 Standb y Mode Thermal Considerations Chapter 8: Sector-Based Program/Erase Protection Sector protection Sector Protection Status at Power-Up 74 Sector Protection Register Sector Protection Register Erase Sector Protection Register Program ........76 Unprotecting Sectors While Sector Protection Enabled Sector Protection Register Limited to 10,000 Program/Erase Cycles 78 Sector Protection Register Read 78 Sector Protection Enable Sector Protection Disable Sector Lockdown Sector Lockdown program .....,....80 Sector lockdown register Sector lockdown register Read 82 Www.xuinX.com Spartan -3AN In-System Flash User Guide UG333(v2. 1)January 15, 2009 xXL|NX° Chapter 9: Security Register Security register.… Security Register Program Security Register Read Appendix A: Optional Power-of-2 Addressing Mode How to Determine the Current Addressing Mode 垂番番 Permanently Changing to the Power-of-2 Addressing Mode Power-of-2 Addressing Mode 88 Power-of-2 Addressing.… Power-of-2 Page Addressing Power-of-2 Block Addressing 990 Power-of-2 Sector Addressing Spartan -3AN In-System Flash User Guide Www.xuinX.com UG333(21) January15,2009 XL|NX° Www.xuinX.com Spartan-3AN In-System Flash User Guide UG333(v2. 1)January 15, 2009 xⅫI№X° Chapter 1 Overview and sPI_ACCEsS Interface Note: This user guide only applies to SpartanB-3AN FPGa designs that access or modify the in system Flash after configuration. This user guide is not required for applications that only use the in- system Flash to configure the FPGA For Spartan-3AN FPGA configuration information, see UG332: Spartan-3 Generation Configuration User Guide partan-3AN FPGAs include abundant In-System Flash(ISF) memory. The IsF memory ISF memory is primarily designed to automatically configure the FPGa when poweris o array appears to a Spartan-3AN FPGA application as SPI-based serial Flash memory. TI applied or whenever the PROG_B pin is pulsed Low. However, the ISF memory array is large enough to store two complete, uncompressed FPGA configuration bitstreams. Using the Multiboot feature, the FPGa application can selectively choose between the two designs or reserve one image as a fail-safe image for live in-system Flash updates additional nonvolatile data for the FPGA application, such as MicroBlazeTM processor code, serial numbers Ethernet mac Ids, graphic images message templates and so In-System Flash Summary Table 1-1, page 8 summarizes the key attributes and capabilities of the ISF memory. The remainder of this user guide describes these features and capabilities in greater detail The table also summarizes the amount of Flash memory available to the FpGa application depending on the number of design options How many FPGA configuration bitstreams are stored in the ISF array? Most applications store a single FPGA configuration bitstream, leaving the remaining space for nonvolatile user data Optionally, each Spartan-3AN FPGA can store two uncompressed MultiBoot configuration images, which reduces the amount of Flash memory available to the application Does the FPGA application use the ISF memory's Sector Protect or Sector Lockdown features to protect iSF memory contents? Without using the sector-based data protection features, user application data can be stored in the next available page location following the FPGa bitstream(page ne If the application uses the sector-based data protection features, then user application data is typically aligned to the next sector boundary(sector aligned) Spartan-3anFpgaIn-systemFlashUserGuidewww.xilinx.com UG333(21) January15,2009 Chapter 1: Overview and SPl_ACCESS Interface XL|NX° Table 1-1: In-System Flash Memory Summary Spartan-3AN FPGA Description 3S50AN 3S200AN3S400AN 3S700AN 3S1400AN n-System Flash(ISF)memory bits 108134443253764325376865075217301504 (1M+) (4M+) (4M+) (8M+) (16M+) SRAM page buffers 2 2 Default Addressing Mode page sizc(bytes) 264 26 264 528 Optional Power-of-2 Addressing Mode page size(bytes)256 256 256 256 512 Pages 512 2.048 2,048 4,096 4,096 Blocks 64 256 256 512 512 Sectors Pages per block 8 8 8 8 Pages pcr Sector 128 256 256 56 256 Bytes per block 2.112 2,112 2,112 2,112 4,224 Bytes per Sector 33,792 67584 67,584 67584 135,168 FPGA configuration bitstream size (uncompressed) 43731211961281,8856027326404755,296 Pages required for FPga bitstream Default 208 567 894 1,294 1126 always starting at page 0 Power-of-2 585 922 1,335 1,161 Page Aligned User Data(maximizes available data space but limits Sector Protect, Sector Lockdown features) Pages available for user application beyond FPGa configuration bitstream, data aligned to next page 304 1,481 1,154 2802 2970 boundary, Default Addressing Mode Total Flash memory bits available for user application, 64204831278722,437,248591782412,545280 (627K Default Addressing modc 354K)(2,380K)(5779K)(12251K) (061M)(2.98M)(2.32M)(564M)(196M) Sector Aligned User Data(user data aligned to sectors for Sector Protect, Sector Lockdown features) Sectors required per uncompressed FPGa bitstream 6 Sectors available for user application beyond FPGA configuration bitstream, aligned to next sector 10 11 ndary Total bits available for user applicalion in remaining 54067227033602162,6885,40672011894784 sectors, Default Addressing Mode (528K)(2,640K)(2,112K)(⑤5,280K)(1616K) (.5M)(257M)(2.06M)(515M)(1.34M) MultiBoot FPGA Configuration Maximum number of uncompressed MultiBoot FPGA configuration images Total sectors available for user application, beyond Multi Boot FPGa configuration bitstreams Total Flash memory bits available for user application, 1,081,344 2,162,6886488064 beyond MultiBoot FPGA configuration bitstreams (1,056K) (2,112K)(6,336K) sector aligned, Default Addressing Mode (1.03M) (2.06M)(6.18M) www.xilinx.comSpartan-3anFpgaIN-systemFlashUserGuide UG333(v2. 1)January 15, 2009 xXL|NX° Accessing In-System Flash Memory After Configuration Accessing In-System Flash Memory After Configuration SPI ACCESS Design Primitive After the FPGA configures, the application loaded into the FPGA can access the ISF memory using a special design primitive called SPI_ACCESS, shown in Figure 1-1. All data accesses to and from the IsF memory are performed using an SPI serial protoco Neither the spartan 3AN fPGA itself nor the spi access primitive includes a dedicated SPI master controller. Instead, the control logic is implemented using the FPGas programmable logic resources. The SPI_ ACCESS primitive essentially connects the FPGA application to the In-System Flash memory array SPI ACCESS MOS CSB CLK Figure 1-1: SPL_ACCESS Primitive(only available on Spartan-3AN FPGAs) Table 1-2 describes the connections to the SPI_ACCESS primitive. The serial data lines are names relating to the logic that drives the data. The FPGA application is always the Master of each sPI transaction; the isf memory is always the slave Table 1-2: SPl ACCESS Primitive Connections Port name Direction Function MISO Output Master Input, Slave Output Serial data output from the ISF memory array back to the FPGA logic. MOSI Master Output, Slave Input Serial data input to the isF P memory array from the FpGa logic CSB Input Active-Low chip-enable to isf memory array driven by FPGA logic CLK nbu Clock input to ISF memory array, driven by FPGa logic Table 1-3 describes the available attributes for the spi access primitive Table 1-3 SPl ACcEsS Primitive Attributes Attribute ype Allowed Values Default Description SIM DEVICE String "3S50AN" UNSPECIFIED" Specifies the target device so that the proper 3S200AN", size sPi memory is used. This attributes 3S400AN〃 required to be set 3S700AN 3S1400AN SIM USER ID 64-byte Any 64-byte hex All locations Specifies the programmed USER ID in the Hex value value default to OxFF Security Register for the SPI Memory Spartan-3anFpgaIn-systemFlashUserGuidewww.xilinx.com 9 UG333(21) January15,2009 Chapter 1: Overview and SPl_ACCESS Interface XL|NX° Table 1-3: SPl_ACCESS Primitive Attributes(Continued) Attribute Type Allowed Values Default Description SIM MEM FILE String Specified file and NONE Optionally specifies a hex file containing the directory name initialization memory content for the SPl Memory SIM_FACTORY_ID 64-byte Any 64-byte Hex All locations Specifies the unique identifier value in the Hex value value default to 0x00 Security Register for simulation purposes the actual hardware value will be specific to the particular device used). See"Security Register" in Chapter 9 SIM_DELAY__TYPE String ACCURATE",“ SCALED Scales down some timing delays for faster ISCALED simulation run. "ACCURATE"=timing and delays consistent with datasheet specs SCALED"=timing numbers scaled back to run faster simulation behavior not affected HDL Instantiation Examples The SPI_ACCESS design primitive must be instantiated in an HDL design; it cannot be ferred by the logic synthesis softwa Caution! Only a subset of the commands available in hardware are supported in simulation for the SPl_ACCESS primitive. Please see the Simulation Support section for a list of these commands VHDL The SPi_ACCeSS primitive requires that the Xilinx Unisim Library be declared. Instantiate the SPI_ACCESS component and connect it to the other signals in the design Xilinx Unisim Library The Xilinx Unisim library includes definitions for all the Spartan-3AN FPGA design primitives, including the SPI_ACCESS primitive. Declare the Unisim library before the entity declarati library UNISIM; use UNISIM. vc nts, all entity XXxx is Instantiate SPl ACCESS Primitive Instantiate the spi access design primitive after the architecture declaration Connect each of the four sPi access ports to a signal name in the FPGA appl lication architecture Behavioral of XXXX is begi SPT ACCESS inst SPI access generic map SIM DEV工CE=>"3s700AN p。 rt map( MISO = MISo signal 1-bit SPI output data MOSI = MOSI signal 1-bit SPI input data 10 www.xilinx.comSpartan-3anFpgaIN-systemFlashUserGuide UG333(v2. 1)January 15, 2009

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