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ad735 模型 pspice 详细配置 ad735 模型 pspice 详细配置
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* AD734 SPICE Macro-model 4/92, Rev. B
* AAG / PMI
*
* Revision History:
* Removed input signal current compensation: GX1,GY1,GZ1
* Added Isy vs. Vsy
*
* Copyright 1992 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* X1
* | X2
* | | UO
* | | | U1
* | | | | U2
* | | | | | Y1
* | | | | | | Y2
* | | | | | | | VN
* | | | | | | | | ER
* | | | | | | | | | Z2
* | | | | | | | | | | Z1
* | | | | | | | | | | | W
* | | | | | | | | | | | | DD
* | | | | | | | | | | | | | VP
* | | | | | | | | | | | | | |
.SUBCKT AD734 10 11 49 50 51 20 21 200 58 31 30 77 54 100
*
* AAG / PMI
*
* Revision History:
* Removed input signal current compensation: GX1,GY1,GZ1
* Added Isy vs. Vsy
*
* Copyright 1992 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* X1
* | X2
* | | UO
* | | | U1
* | | | | U2
* | | | | | Y1
* | | | | | | Y2
* | | | | | | | VN
* | | | | | | | | ER
* | | | | | | | | | Z2
* | | | | | | | | | | Z1
* | | | | | | | | | | | W
* | | | | | | | | | | | | DD
* | | | | | | | | | | | | | VP
* | | | | | | | | | | | | | |
.SUBCKT AD734 10 11 49 50 51 20 21 200 58 31 30 77 54 100
*
EREF 300 0 POLY(2) 100 0 200 0 (0,0.5,0.5)
*
* X INPUT STAGE & POLE AT 40 MHz
*
CINX 10 11 2E-12
IBX1 10 0 DC 50E-9
IBX2 11 0 DC 50E-9
EOSX 12 10 POLY(1) 18 300 15E-3 1
RX1 12 13 25E3
RX2 13 11 25E3
*
GX1 300 14 12 11 1E-6
RX3 14 300 9.995E5
CX1 14 300 3.9809E-15
VX1 100 15 DC 3.1875
DX1 14 15 DX
VX2 16 200 DC 3.1875
DX2 16 14 DX
*
* X INPUT STAGE COMMON-MODE REJECTION AND ZERO 40 kHz
*
ECMX 17 300 13 300 56.234
RCMX1 17 18 1E6
CCMX 17 18 3.9789E-12
RCMX2 18 300 1
*
* Y INPUT STAGE & POLE AT 40 MHz
*
CINY 20 21 2E-12
IBY1 20 0 DC 50E-9
*
* X INPUT STAGE & POLE AT 40 MHz
*
CINX 10 11 2E-12
IBX1 10 0 DC 50E-9
IBX2 11 0 DC 50E-9
EOSX 12 10 POLY(1) 18 300 15E-3 1
RX1 12 13 25E3
RX2 13 11 25E3
*
GX1 300 14 12 11 1E-6
RX3 14 300 9.995E5
CX1 14 300 3.9809E-15
VX1 100 15 DC 3.1875
DX1 14 15 DX
VX2 16 200 DC 3.1875
DX2 16 14 DX
*
* X INPUT STAGE COMMON-MODE REJECTION AND ZERO 40 kHz
*
ECMX 17 300 13 300 56.234
RCMX1 17 18 1E6
CCMX 17 18 3.9789E-12
RCMX2 18 300 1
*
* Y INPUT STAGE & POLE AT 40 MHz
*
CINY 20 21 2E-12
IBY1 20 0 DC 50E-9
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