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ISE的Block_Ram的设计流程（附xilinx block memory datasheet).rar （2个子文件）

blk_mem_gen_ds512.pdf 2.77MB

ISE_的Block_RAM的设计流程.ppt 474KB

DS512 April 24, 2009 www.xilinx.com 1

Product Specification

States and other countries. All other trademarks are the property of their respective owners

Introduction

The Xilinx LogiCORE™ IP Block Memory Generator

core is an advanced memory constructor that generates

area and performance-optimized memories using

embedded block RAM resources in Xilinx FPGAs.

Available through the CORE Generator™ software,

users can quickly create optimized memories to

leverage the performance and features of block RAMs

in Xilinx FPGAs.

Features

• Generates Single-port RAM, Simple Dual-port

RAM, True Dual-port RAM, Single-port ROM, and

Dual-port ROM

• Performance up to 450 MHz

• Supports data widths from 1 to 1152 bits and

memory depths from 2 to 9M words (limited only

by memory resources on selected part)

• Supports configurable port aspect ratios for dual-

port configurations and read-to-write aspect ratios

in Virtex®-4, Virtex-5 and Virtex-6 FPGAs

• Optimized algorithms for minimum block RAM

resource utilization or low power utilization

• Configurable memory initialization

• Supports individual write enable per byte in

Virtex-6, Virtex-5, Virtex-4, Spartan®-6, and

Spartan-3A DSP with or without parity

• Optimized VHDL and Verilog behavioral models

for fast simulation times; structural simulation

models for precise simulation of memory

behaviors

• Selectable operating mode per port: WRITE_FIRST,

READ_FIRST, or NO_CHANGE

• Supports built-in Hamming Error Correction

Capability (ECC) for Virtex-5 and Virtex-6 devices,

and associated error injection pins in Virtex-6 to

insert single and double bit errors

• Supports pipelining of DOUT bus for improved

performance in specific configurations

• Smaller primitive configurations in Spartan-6

devices with the introduction of new 9K

primitives.

• Lower data widths for Virtex-6 devices in SDP

mode.

• Choice of reset priority for output registers

between priority of SR (Set Reset) or CE (Clock

Enable) in Spartan-6 and Virtex-6 families.

• Asynchronous reset in Spartan-6 devices.

Block Memory Generator v3.1

DS512 April 24, 2009 Product Specification

LogiCORE™ IP Facts

Core Specifics

Supported Device

Family

Virtex-6, Virtex-5, Virtex-4,

Spartan-6, Spartan-3E, Spartan-3,

Spartan-3A/3AN/3A DSP

Block RAM Varied, based on core parameters

DCM None

BUFG None

IOBs/RocketIO™

Transceivers

None

PPC None

IOB-FF/TBUFs None

Provided with Core

Documentation

Product Specification

Migration Guide

(1)

1. The Migration Guide provides instructions for converting designs

that contain instances of either Legacy LogiCORE IP 6.x Single or

Dual Port Block Memory, or older versions of LogiCORE Block

Memory Generator to blocks of the latest version of the LogiCORE

Block Memory Generator.

Design File

Formats

NGC Netlist

Design Tool Requirements

Xilinx

Implementation

Too ls

ISE® v11.1

Simulation

Mentor Graphics® ModelSim®: v6.4b and above

VHDL Structural

Verilog Structural

VHDL Behavioral

(2)

Verilog Behavioral

(2)

2. Behavioral models do not precisely model collision be-

havior. See "Simulation Models," page 32 for details.

Synthesis

XST

Support

Provided by Xilinx, Inc.

Block Memory Generator v3.1

2 www.xilinx.com DS512 April 24, 2009

Product Specification

Overview

The Block Memory Generator core uses embedded Block Memory primitives in Xilinx FPGAs to extend

the functionality and capability of a single primitive to memories of arbitrary widths and depths.

Sophisticated algorithms within the Block Memory Generator core produce optimized solutions to pro-

vide convenient access to memories for a wide range of configurations.

The Block Memory Generator has two fully independent ports that access a shared memory space. Both

A and B ports have a write and a read interface. In Virtex-6, Virtex-5 and Virtex-4 FPGA architectures,

all four interfaces can be uniquely configured, each with a different data width. When not using all four

interfaces, the user can select a simplified memory configuration (for example, a Single-Port Memory

or Simple Dual-Port Memory), allowing the core to more efficiently use available resources.

The Block Memory Generator is not completely backward-compatible with the Single-Port Block Mem-

ory and Dual-Port Block Memory cores; for information about the differences, see "Compatibility with

Older Memory Cores," page 50.

Applications

The Block Memory Generator core is used to create customized memories to suit any application. Typ-

ical applications include:

• Single-port RAM: Processor scratch RAM, look-up tables

• Simple Dual-port RAM: Content addressable memories, FIFOs

• True Dual-port RAM: Multi-processor storage

• Single-port ROM: Program code storage, initialization ROM

• Dual-port ROM: Single ROM shared between two processors/systems

Feature Summary

Memory Types

The Block Memory Generator core uses embedded block RAM to generate five types of memories:

• Single-port RAM

• Simple Dual-port RAM

• True Dual-port RAM

• Single-port ROM

• Dual-port ROM

For dual-port memories, each port operates independently. Operating mode, clock frequency, optional

output registers, and optional pins are selectable per port. For Simple Dual-port RAM, the operating

modes are not selectable; they are fixed as READ_FIRST. See "Collision Behavior," page 16 for addi-

tional information.

Selectable Memory Algorithm

The core concatenates block RAM primitives according to one of the following algorithms:

• Minimum Area Algorithm: The memory is generated using the minimum number of block RAM

primitives. Both data and parity bits are utilized.

DS512 April 24, 2009 www.xilinx.com 3

Product Specification

Block Memory Generator v3.1

• Low Power Algorithm: The memory is generated such that the minimum number of block RAM

primitives are enabled during a read or write operation.

• Fixed Primitive Algorithm: The memory is generated using only one type of block RAM

primitive. For a complete list of primitives available for each device family, see the data sheet for

that family.

Configurable Width and Depth

The Block Memory Generator can generate memory structures from 1 to 1152 bits wide, and at least two

locations deep. The maximum depth of the memory is limited only by the number of block RAM prim-

itives in the target device.

Selectable Operating Mode per Port

The Block Memory Generator supports the following block RAM primitive operating modes: WRITE

FIRST, READ FIRST, and NO CHANGE. Each port may be assigned an operating mode.

Selectable Port Aspect Ratios

The core supports the same port aspect ratios as the block RAM primitives:

• In all supported device families, the A port width may differ from the B port width by a factor of 1,

2, 4, 8, 16, or 32.

• In Virtex-6, Virtex-5 and Virtex-4 FPGA-based memories, the read width may differ from the write

width by a factor of 1, 2, 4, 8, 16, or 32 for each port. The maximum ratio between any two of the

data widths (

DINA, DOUTA, DINB, and DOUTB) is 32:1.

Optional Byte-Write Enable

In Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3A/3A DSP FPGA-based memories, the Block

Memory Generator core provides byte-write support for memory widths of 8-bit (no parity) or 9-bit

multiples (with parity).

Optional Output Registers

The Block Memory Generator provides two optional stages of output registering to increase memory

performance. The output registers can be chosen for port A and port B separately. The core supports the

Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3A DSP embedded block RAM registers as well as

registers implemented in the FPGA fabric. See "Output Register Configurations," page 56 for more

information about using these registers.

Optional Pipeline Stages

The core provides optional pipeline stages within the MUX, available only when the registers at the

output of the memory core are enabled and only for specific configurations. For the available configu-

rations, the number of pipeline stages can be 1, 2, or 3. For detailed information, see "Optional Pipeline

Stages," page 20.

Block Memory Generator v3.1

4 www.xilinx.com DS512 April 24, 2009

Product Specification

Optional Enable Pin

The core provides optional port enable pins (ENA and ENB) to control the operation of the memory.

When deasserted, no read, write, or reset operations are performed on the respective port. If the enable

pins are not used, it is assumed that the port is always enabled.

Optional Set/Reset Pin

The core provides optional set/reset pins (RSTA and RSTB) for each port that initialize the read output

to a programmable value.

Memory Initialization

The memory contents can be optionally initialized using a memory coefficient (COE) file or by using the

default data option. A COE file can define the initial contents of each individual memory location, while

the default data option defines the initial content of all locations.

Built-in Hamming Error Correction Capability

Simple Dual-port RAM memories support the FPGA Hamming Error Correction Capability (ECC) of

the Virtex-6 and Virtex-5 FPGA block RAM primitives. The ECC memory automatically detects single-

and double-bit errors, and is able to auto-correct the single-bit errors.

Simulation Models

The Block Memory Generator core provides behavioral and structural simulation models in VHDL and

Verilog for both simple and precise modeling of memory behaviors, for example, debugging, probing

the contents of the memory, and collision detection.

Functional Description

The Block Memory Generator is used to build custom memory modules from block RAM primitives in

Xilinx FPGAs. The core implements an optimal memory by arranging block RAM primitives based on

user selections, automating the process of primitive instantiation and concatenation. Using the CORE

Generator Graphical User Interface (GUI), users can configure the core and rapidly generate a highly

optimized custom memory solution.

Memory Type

The Block Memory Generator creates five memory types: Single-port RAM, Simple Dual-port RAM,

True Dual-port RAM, Single-port ROM, and Dual-port ROM. Figure 1 through Figure 5 illustrate the

signals available for each type. Optional pins are displayed in italics.

For each configuration, optimizations are made within the core to minimize the total resources used.

For example, a Simple Dual-port RAM with symmetric ports can utilize the special Simple Dual-port

RAM primitive in Virtex-5 devices, which can save as much as fifty percent of the block RAM resources

DS512 April 24, 2009 www.xilinx.com 5

Product Specification

Block Memory Generator v3.1

for memories 512 words deep or fewer. The Single-port ROM allows read access to the memory space

through a single port, as illustrated in Figure 1.

The Dual-port ROM allows read access to the memory space through two ports, as shown in Figure 2.

X-Ref Target - Figure 1

Figure 1: Single-port ROM

X-Ref Target - Figure 2

Figure 2: Dual-port ROM

Single-Port ROM

ADDRA

ENA

RSTA

CLKA

DOUTA

REGCEA

Dual-Port ROM

ADDRA

ENA

RSTA

CLKA

DOUTA

DOUTB

REGCEA

ADDRB

ENB

RSTB

CLKB

REGCEB

评论收藏

内容反馈

xiaohuochai123

2012-05-19

不是很详细。还好啦~~~
wjxxiaomao

2013-04-30

还是不错的就是英文的太难看了
sunjingpinga

2014-06-06

挺不错的，非常有参考价值
零落成雨

2014-04-15

资料还行，一直在找，谢谢！
艾迪

2013-12-21

一般般，不建议下载PPT百度文库都找得到的

前往

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