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armv8-a cpu手册,官方英文原版,64位和32位的都有讲,适合想要深入学习arm体系架构的人阅读
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All rights reserved Arn Limited Companly 02557590 registered in England 110 Fulbourn Road, Cambridge, England CB1 9NJ LES-PRE-20349 In this document, where the term arm is used to refer to the company it means"Arm or any of its subsidiaries as appropriate Note The term ARM can refer to versions of the arm architecture. for example armv8 refers to version 8 of the arm architecture. The context makes it clear when the term is used in this way This document describes only the armvg-A architecture profile For the behaviors required by the previous version of this architecture profile, ARMV7-A, see the ARM Architecture Reference Manual, ARMv7-A and ARMv 7-R edition Confidentiality Status This document is Nonl-Confidential. The right LO use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that arm delivered this document to Product Status The information in this document is final that is for a deve loped product Web address http://www.arm.com Limitations of this issue This issue of the aRMv8 Architecture Reference Manual contains many improvements and corrections. Validation of this document has identified the following issues that arm will address in future issues Appendix K12 ARM Pseudocode Definition requires further review and update. Since this appendix is informative, rather than being part of the architecture specification, this does not affect the quality status of this release ARM DDI 0487C Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. D121917 Non-Confidential Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. ARM DDI 0487C a Non-Confidential D121917 Contents ARM Architecture Reference Manual arMv8 for ARMV8-A architecture profile Preface About this manual XVI Using this manual XVIll Conventions 1aaaa“面11面 ∴XX|V Additional reading Feedback Part a ARMV8 Architecture Introduction and overview Chapter a1 Introduction to the army architecture al.1 About the arm architecture A1-32 A1.2 Architecture profiles A1-34 A1.3 ARMv8 architectural concepts A1-36 A1.4 Supported data type A1-40 A1.5 Advanced SIMD and floating-point support A1-50 A1.67 he ARM memory model……… A156 Al.7 ARMv8 architecture extensions A1-57 Part B The AArch64 Application Level Architecture Chapter B The AArch64 Application Level Programmers' Model B1.1 About the Application level programmers model .B1-76 B1.2 Registers in Aarch 64 Execution state B177 B1.3 Software control features and elo B182 ARM DDI 0487C Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. D121917 Non-Confidential Contents Chapter B2 The AArch64 Application Level Memory Model B2. 1 About the ARM memory model B286 B2.2 Atomicity in the ARM architecture B2-88 B2. 3 Definition of the ARMv8 memory model B2-92 B2. 4 Caches and memory hierarchy B2-104 B2.5 Alignment support B2-109 B2.6 Endian support B2-111 B2.7 Memory types and attributes B2-114 B2.8 Mismatched memory attributes ..B2-125 B2. 9 Synchronization and semaphores B2-128 Part c The aarch64 Instruction set Chapter C1 The a64 Instruction set Cl1 About the a64 instruction set C1-142 C1.2 Structure of the A64 assembler language C1-143 C1.3 Address generation....... C1-149 C1, 4 Instruction aliases ..C1-152 Chapter C2 About the A64 Instruction Descriptions C2. 1 Understanding the a64 instruction descriptions C2-154 C2.2 General information about the a64 instruction descriptions C2-157 Chapter C3 A64 Instruction Set Overview C3.1 Branches, Exception generating, and System instructions C3-162 C3.2 Loads and stores C3-169 C3.3 Data processing-immediate C3-185 C3.4 Data processing-register C3-190 C3.5 Data processing - SIMD and floating-point C3-198 Chapter C4 A64 Instruction Set Encoding C4. 1 A64 instruction set encoding C4-224 Chapter C5 The A64 System Instruction Class C5. 1 The System instruction class encoding space C5-328 C52 Special-purpose registers C5-339 C5. 3 A64 System instructions for cache maintenance C5-409 C54 A64 system instructions for address translation C5432 C55 A64 System instructions for TLB maintenance C5459 Chapter C6 A64 Base Instruction Descriptions c6. 1 About the a64 base instructions .:“ C6-524 C62 Alphabetical list of A64 base instructions C6-526 Chapter c7 A64 Advanced SIMD and Floating-point Instruction Descriptions C7. 1 About the A64 SIMD and floating-point instructions C7-1006 C7.2 Alphabetical list of A64 Advanced SIMD and floating-point instructions ......C7-1008 Part d The AArch64 System Level Architecture Chapter D1 The AArch64 System Level Programmers' Model D1.1 Exception levels D1-1850 D1.2 EXception terminology ..... D1-1851 D1.3 Execution state D1-1853 D1. 4 Security state D1-1854 Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. ARM DDI 0487C a Non-Confidential D121917 Contents D1.5 Virtualization D1-1856 D1.6 Registers for instruction processing and exception handling D1-1859 D1.7 Process state, PStATE D1-1865 D1. 8 Program counter and stack pointer alignment D11868 D19 Reset 11870 D1.10 Exceptio D1-1874 D1.11 Exception return D11883 D1.12 The Exception level hierarchy D1-1887 D1.13 Synchronous exception types, routing and priorities ∴D1-1894 D1.14 Asynchronous exception types, routing, masking and priorities D1-1902 D1.15 Configurable instruction enables and disables and trap controls D1-1910 D1.16 System calls D1-1953 D1.17 Mechanisms for entering a low-power state D1-1954 D1.18 Self-hosted debug 1-1959 D1.9 The Performance monitors extension D1-1961 D1. 20 Interprocessing D1-1962 D1.21 The effect of implementation choices on the programmers'model...... D1-1974 Chapter D2 AArch64 Self-hosted Debug D2.1 About self-hosted debug D2-1980 D2.2 The debug exception enable controls 2-1984 D2.3 Routing debug exceptions .D2-1985 D2. 4 Enabling debug exceptions from the current Exception level and Security state D2-1987 D2.5 The effect of powerdown on debug exceptions D2-1989 D2.6 Summary of the routing and enabling of debug exceptions D2-1990 D2.7 Pseudocode description of debug exceptions D21992 D2.8 Breakpoint Instruction exceptions .D2-1993 D2.9 Breakpoint exceptions D2-1995 D2. 10 Watchpoint exceptions D2-2016 D2. 11 Vector Catch exceptions D2-203 D2. 12 Software Step exceptions D2-2032 D2.13 Synchronization and debug exceptions D2-2046 Chapter D3 The Aarch64 System Level Memory Model D3. 1 about the memory system architecture .D3-2048 D3.2 Address space D3-2049 D3.3 Mixed-endian support .“ D3-2050 D3.4 Cache support D3205′ D3.5 External aborts D32074 D3.6 Memory barrier instructions D3-2076 D3.7 Pseudocode description of general memory system instructions D3-2077 Chapter D4 The AArch64 Virtual Memory System Architecture D4.1 About the virtual Memory System Architecture(VMSA)…………D4-2082 D4.2 The VmsAv8-64 address translation system D4-2091 D4.3 VMSAv8-64 translation table format descriptors ∴D4-2143 D4.4 Memory access control D4-2155 D4.5 Memory region attributes D4-2174 D4. 6 Virtualization host extensions D4-2183 D4,7 Nested virtualization D4-2188 D4.8 VMSAv8-64 memory aborts D4-219 D4.9 Translation Lookaside Buffers (tlBs). ∴D4-2201 D4.10 TLB maintenance requirements and the tlB maintenance instructions ... D4-2207 D4.11 Caches in a VMSAv8-64 implementation ... D4-2221 Chapter D5 The Performance monitors extension D5.1 About the performance monitors D5-2226 ARM DDI 0487C Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. D121917 Non-Confidential Contents D52 Accuracy of the Performance Monitors…… D5-2228 D53 Behavior on overflow D5-2230 D5. 4 Attributability D5-2232 D5.5 Effect of el3 and El2 D5-2233 D5.6 Event filtering… D52235 D57 Performance Monitors and debug state D5-2237 D5 8 Counter enables D5-2238 D5.9 Counter access D5-2239 D5. 10 PMU events and event numbers D5-2240 D5. 11 Performance Monitors Extension registers ..... D5-2268 Chapter D6 The Statistical Profiling Extension D6. 1 Statistical Profiling D6-2272 D6.2 Programmers Model D6-2280 D6 3 Enable and Filtering controls D6-2283 D6.4 Profiling Buffer management interrupt D6-2289 Ch later D7 Statistical Profiling Extension Sample Record Specification D7.1 About the Statistical Profiling EXtension Sample Records D7-2296 D7.2 Alphabetical list of Statistical Profiling EXtension packets .......... D7-2299 Chapter D8 The generic Timer in AArch64 state D8. 1 About the generic timer D8.2 The Aarch64 view of the generic Timer D82326 Chapter D9 AArch 64 System Register Encoding D9.1 The System register encoding space D9-2332 D9.2 op0==0b10, Moves to and from debug and trace System registers D9-2333 D9. 3 op0==0b11, Moves to and from non-debug System registers, Special-purpose registers D92335 Chapter d10 AArch64 System Register Descriptions D10.1 About the AArch64 System registers D10-2348 D10.2 General system control registers D10-2357 D10.3 Debug registers... D10-2765 D10.4 Performance Monitors registers D10-2840 D10.5 Statistical Profiling Extension registers D10-2885 D10.6 Generic Timer registers D10-2917 Part E The AArch 32 Application Level Architecture Chapter E1 The aarch32 Application Level Programmers'Model E11 About the Application level programmers' model E1-2978 E1.2 The Application level programmers model in AArch32 state E1-2979 E13 Advanced simd and floating- point instructions…….…………….1-2990 E1.4 About the AArch32 System register interface E13001 E1.5 Exceptions E13002 Chapter E2 The AArch32 Application Level Memory Model E2.1 About the ARM memory model 2-3004 E2. 2 Atomicity in the ARM architect E23006 E2.3 Definition of the armv& memory model .E2-3011 E2.4 Caches and memory hierarchy E2-3022 E2.5 Alignment support E2-3027 E2.6 Endian support E2-3029 E2.7 Memory types and attributes E2-3032 E2.8 Mismatched memory attributes E2-3042 Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. ARM DDI 0487C a Non-Confidential D121917 Contents E2.9 Synchronization and semaphores E2-3045 Part F The aarch32 Instruction sets Chapter F1 The aarch 32 Instruction Sets Overview F1.1 Support for instructions in different versions of the ARM architecture F13058 F1.2 Unified Assembler Language F13059 F1.3 Branch instructions F1-3061 1.4 Data-proces F1-3062 F1.5 PStaTE and banked register access instructions F1-3070 F1.6 Load /store instructions F1-3071 F1.7 Load/store multiple instructions F1-3074 F1. 8 Miscellaneous instructions F13075 F1.9 Exception-generating and exception-handling instructions F1-3077 F1.10 System register access instructions F13079 F1.11 Advanced SIMD and floating-point load/store instructions F13080 F1.12 Advanced SIMD and floating-point register transfer instructions F1-3082 F1.13 Advanced SIMD data-processing instructions F1-3083 F1.14 Floating-point data-processing instructions F1-3093 Chapter F2 About the T32 and A32 Instruction Descriptions F2.1 Format of instruction descriptions .... F23096 F2.2 Standard assembler syntax fields F23100 F2,3 Conditional execution F23101 F2. 4 Shifts applied to a register F2-3104 F2.5 Memory accesses F2-3106 F2.6 Encoding of lists of general-purpose registers and the pc F2-3107 F2.7 General information about the T32 and A32 instruction descriptions F2-3108 F2.8 Additional pseudocode support for instruction descriptions F2-3121 F2. 9 Additional information about Advanced SIMD and floating-point instructions. F2-3122 Chapter F3 T32 Instruction Set Encoding F3. 1 T32 instruction set encoding ... F3-3130 F3.2 About the T32 Advanced SIMD and floating-point instructions and their encoding F33196 Chapter F4 A32 Instruction Set Encoding F4.1 A32 instruction set encoding F4-3198 F4.2 About the A32 Advanced SIMD and floating-point instructions and their encoding F4-3256 Chapter F5 T32 and A32 Base Instruction Set Instruction Descriptions F5.1 Alphabetical list of T32 and A32 base instruction set instructions ...... F5-3258 F52 Encoding and use of banked register transfer instructions F5-3928 Chapter F6 T32 and A32 Advanced SIMD and Floating-point Instruction Descriptions F6.1 phabetical list of Advanced SIMd and floating- point instructions F63934 Part The AArch32 System Level Architecture Chapter G1 The AArch32 System Level Programmers'Model G1.1 About the AArch32 System level programmers' model .G14590 G1.2E G1.3 Exception terminology G1-4592 G1.4 Execution state G1-4594 G1.5 Instruction Set stat G1-4596 ARM DDI 0487C Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. D121917 Non-Confidential Contents G1.6 Security state G1-4597 G1.7 Security state, EXception levels, and AArch32 execution privilege G1-4600 G18 Virtualization ..G1-4602 G1. 9 AArch32 PE modes, and general-purpose and Special-purpose registers.. G1-4604 G1. 10 Process state PSTatE G1-4614 G1,12 Handling exceptions that are taken to an Exception level using AArch J ...G1-4620 G1.11 Instruction set states ..G14622 G1.13 Routing of aborts taken to AArch32 state G1-4642 G1.14 Exception return to an Exception level using AArch32…….….…….G1-4645 G1.15 Asynchronous exception behavior for exceptions taken from AArch32 state. G1-4650 G1.16 AArch32 state exception descriptions G1-4661 G1.17 Reset into aarch 32 state G1-4684 G1.18 Mechanisms for entering a low-power state G1-4688 G1.19 The AArch32 System register interface G1-4693 G1.20 Advanced SIMD and floating-point support G1-4696 G1. 21 Configurable instruction enables and disables, and trap controls ∴.G1-4702 Chapter G2 AArch32 Self-hosted Debug G2. 1 About self-hosted debug G2-4738 G2.2 The debug exception enable controls G2-4742 G2. 3 Routing debug exceptions .G2-4743 G2.4 Enabling debug exceptions from the current Privilege level and security state G24745 G2.5 The effect of powerdown on debug exceptions G2-4747 G2.6 Summary of permitted routing and enabling of debug exceptions ∴G24748 G2.7 Pseudocode description of debug exceptions G2-4750 G2.8 Breakpoint Instruction exceptions G24751 G29 Breakpoint exceptions…… G2-4754 G2. 10 Watchpoint exceptions .G2-478 G2. 11 Vector Catch exceptions G2-4795 G2.12 Synchronization and debug exceptions G2-4803 Chapter G3 The AArch32 System Level Memory Model G3.1 About the memory system architecture................... G3-4806 G3.2 Address space G3-4807 d- endian supp G3-4808 G3.4 AArch 32 cache and branch predictor support G34809 G3.5 System register support for IMPLEMENTATION DEFINED memory features G3-4834 G3. 6 External aborts 3-4835 G3.7 Memory barrier instructions 6G34837 G3. 8 Pseudocode description of general memory system instructions G3-4838 Chapter G4 The AArch32 virtual Memory System Architecture G4,1 About Vmsay8-32 G4-4842 G4.2 The effects of disabling address translation stages on Vmsav8-32 behavior G4-4850 G4 3 Translation tables G4-4854 G4. 4 The VMSAv8-32 Short-descriptor translation table format .G44859 G4.5 The VMSAv8-32 Long-descriptor translation table format G4-4868 G4.6 Memory access control G4-4888 G4.7 Memory region attributes G4-4899 G4.8 Translation Lookaside Buffers(TLBs G4-4911 G4.9 TLB maintenance requirements G4-4915 G4, 10 Caches in VMsAv8-32 G4-4929 G4.11 VMSAv8-32 memory aborts G4-4932 G4.12 Exception reporting in a VMsAv8-32 implementation G4-4944 G4, 13 Address translation instructions G4-4963 G4.14 Pseudocode description of VMSAv8-32 memory system operations G4-4970 G4.15 About the System registers for VmsAv8-32 G4-4972 G4.16 Functional grouping of VMSAv8-32 System registers G4-4977 X Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. ARM DDI 0487C a Non-Confidential D121917

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qq_30256599 挺全的,就是全英文的
2018-05-24
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