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STM32L151xx,STM32L152xx和STM32L162xx的Flash和EEPROM的编程手册.pdf 介绍 Flash和EEPROM的读写操作
PM0062 Contents 4.1 Alignment error flag 4.4.2 Size error flag 4.4.3 Bus error(Cortex-M3 hardfault or Busfaul 28 Option byte description ■■■■■■■■ 29 5.1 Option byte block programming 32 6 Quick reference to programming/erase functions 33 7 Memory protection∴ 35 7.1 Readout protection(RDP)of the program and data EEPROMs 35 7.1.1 Level 1: memory read protection enabled 7.1.2 Level 2: memory read protection enabled and all debug features disabled 36 7.2 Write protection (WRP)of the program memory 37 7. 3 Write protection error flag ..........37 Interrupts 38 Register description 量■■■■■■■■ 39 9.1 Access control register(FLASH_ACR) ■■ 39 9.2 Program/erase control register(FLASH_PECR) 9.3 Power down key register(FLASH_PDKEYR) 42 9. 4 Program/erase key register(FLASH_ PEKEYR 43 9.5 Program memory key register (FLASH_-PRGKEYR) 43 9.6 Option byte key register(FLASH_OPTKEYR)........... 44 9.7 Status register(FLASH_ SR) 44 9.8 Option byte register(FLASH_OBR) 46 9. 9 Write protection register(FLASH_ WRPRX) 47 9.10 Register map ■■ 48 Revision history 49 DOc ID 16024 ReV 5 3/50 List of tables PM0062 List of tables Table 1. Flash module organization (medium density devices Table 2. Flash module organization(medium+ devices Table 3. Flash module organization(high density devices) Table 4. Number of wait states(WS)according to CPU clock(HCLK) frequency 13 Table 6. Data EEPROM programming times 25 Table 7. Read While Write Summary 6 Table 8 Prohibited operations 28 Table 9. Option byte organization Table 10. Description of the option bytes ...30 Table 11. Programming/erase functions(medium density devices ...33 Table 12. Programming/erase functions(high density devices) .34 Table 13. Flash memory module protection according to RDP and its complement Table 14. Interrupts ,38 Table 15. Register map and reset values 48 Table 16. Document revision history 49 4/50 Doc D 16024 ReV 5 PM0062 List of figures List of figures Figure 1. Flash memory programming overview Figure 2. Sequential 32 bits instructions execution 14 Figure 3. RdP levels ,,,,,,,,36 DOc ID 16024 ReV 5 5/50 Glossary PM0062 Glossa This section gives a brief definition of acronyms and abbreviations used in this document Medium-density devices are STM32L151 xx and STM32L152XX microcontrollers where the program memory density ranges between 64 and 128 Kbytes Medium+ density devices are StM32L151 Xx, STM32L152XX and STM32L162XX icrocontrollers where the program memory density size is 256 Kby Note For CSP64, BGA132, QFP144 packages, the chip follows the characteristics of high density devices with bank 1 containing 192 Kbytes of program flash and 6 Kbytes of data EEPROM and with bank 2 containing 64 kbytes of program flash and 2 kbytes of data EEPROM High-density devices are sTM32L151 xx, sTM32L152xX and STM32L162XX microcontrollers where the program memory density is 384 Kbytes The Cortex-M3 core integrates two debug ports JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the Joint Test Action Group (JTAG) protocol SWD debug port(SWD-DP)provides a 2-pin(clock and data)interface based on the Serial Wire Debug(sWD)protocol For both the jtAG and SWd protocols please refer to the ARM Core Sight on-chip trace and debug documentation Word: data/instruction of 32-bit length Half word: data/instruction of 16-bit length Byte: data of 8-bit length Double word: data of 64-bit length Page: 64 words of program memory Sector: 16 pages( write protection granularity lAP(in-application programming): IAP is the ability to re-program the flash memory of a microcontroller while the user program is running o ICP(in-circuit programming): ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol, the swd protocol or the boot loader while the device is mounted on the user application board I-Code: this bus connects the instruction bus of the cortex-M3 core to the flash instruction interface Prefetch is performed on this bus D-Code: this bus connects the D-Code bus(literal load and debug access)of the Cortex-M3 to the flash data interface Option bytes: pl configuration bits stored in Flash memory OBL: option byte loader AHB: advanced high- performance bus CPU (central processing unit) this term stands for the Cortex-M3 core 6/50 Doc D 16024 ReV 5 PM0062 Introduction Introduction The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the memory module. It implements the erase and program memory operations and the read and write protection mechanisms The Flash memory interface accelerates code execution with a system of instruction prefetch DOc ID 16024 ReV 5 7/50 Main features PM0062 Main features Up to 396 Kbytes total storage capacity Memory organization Up to 384 Kbytes of program memory Up to 12 Kbytes of data EEPROM Up to 8 Kbytes of system memory and 64 bytes of option bytes Dual bank organisation(in high density devices): each bank has up to 192 Kbytes of program memory and 6 Kbytes EEPROM 4 Kbytes of system memory and 32 bytes of option bytes Flash memory interface(FLITF)features Flash module read operations: read access is performed on 64 or 32 bits Flash module program/erase operations Read /write protection Write access is performed on 32 bits Option byte loader Low power mode Flash module in Power down mode when the STM32 L1 5xXx is in Standby mode or Stop mode Flash module can be placed in Power down or Idle mode when the STM32L15XXX is in Sleep mode Flash module can be placed in Power down or ldle mode when the STM32L15XXX is in Run mode Vote The DMa can only access Flash memory module with read operations 8/50 Doc D 16024 ReV 5 PM0062 Flash module organization 3 Flash module organization The memory is organized as Program memory blocks, data EEPROM blocks and information blocks. Table 1, Table 2 and Table 3 show the memory organization granularity. The pages are the erase granularity for the program memory block 3 The program memory block is divided into sectors of 4 Kbytes each, and each sector is further split up into 16 pages of 256 bytes each. The sector is the write protectior The program memory pages can be written using a half page programming or a fast word programming operation Data EEPROM can be erased and written by ● Double word Word/ Fast word Half word /Fast half word Byte/Fast byte During a write/erase operation to the Flash memory(except Half Page programming or Double-word erase/write), any attempt to read the same bank of Flash memory stalls the bus. The read operation is executed correctly once the programming operation is completed. This means that code or data fetches cannot be performed while a write/erase operation is ongoing in the same bank For more details, refer to Section 4.2: Erasing memory on page 18 and Section 4.3 Programming memory on page 20 Note Code execution is not possible from Data EEPROM Table 1. Flash module organization(medium density devices) Block Name Memory addresses Size Page 0 0x08000000-0X080000FF 256 bytes Page 1 0x08000100-0X080001FF 256 bytes Page 2 0x08000200-0x080002FF 256 bytes Sector o Page 3 0x08000300-0x080003FF 256 bytes Page 4 to 7 0x08000400-0×080007FF 1 Kbytes Page 8 to 11 0x08000800-0X08000BFF 1 Kbyte Page 12 to 15 0x08000c00-0X08000FFF 1 Kbyte Program memory Sector 1 0x08001000-0X08001FFF 4 Kbytes Sector 2 0x08002000-0X08002FFF 4 Kbytes Sector 3 0x08003000-0x08003FFF 4 Kbytes Sector 30 0x0801E000-0X0801EFFF 4 Kbytes Sector 31 0x0801F000-0X0801FFFF 4 Kbytes DOc ID 16024 ReV 5 9/50 Flash module organization PM0062 Table 1. Flash module organization(medium density devices)(continued) Block Name Memory addresses Size Data memory EEPROM DATA 0x08080000-0X08080FFF 4096 bytes Page o 0x1FF000000X1FF000FF 256 bytes Page 1 0x1FF00100-0X1FF001FF 256 bytes Page 2 0X1FF00200-0X1FF002FF 256 bytes Page 3 Ox1FF0 0300-OX1FF0 03FF 256 bytes System Information block memory Page 15 Ox1FF0 OF00-OX1FF0 OFFF 256 bytes Option bytes block OPTB 0X1FF80000-0X1FF8000F 16 bytes Table 2. Flash module organization(medium+ devices) Block Name Memory addresses Size Page00×08000000-0X080000FF 256 bytes Page1|0×08000100-0×080001FF 256 bytes Page20×08000200-0x080002FF 256 bytes Sector o Page3|0×08000300-0x080003FF 256 bytes Page4to7|0×08000400×08000F 1 Kbytes Page8to110x08000800-0x08000BFF 1 Kbytes Page12to150×08000c00-0×0800OFFF 1 Kbytes Sector 1 Page16to310×08001000-0×08001FFF 4 Kbytes Sector2Page32to47|0×08002000-0×08002FFF 4 Kbytes Program memory Sector 3 Page 48 to 63 0X0800 3000-0X0800 3FFF 4 Kbytes Sector 30 Page 478 to 0x0801E000-0x0801EFFF 4 Kbytes 495 Sector 31 Page 496 to 0x0801F000-0X0801FFFF 4Kbytes 511 Sector 32 to page 512 to Sector 47 767 0x08020000-0X0802FFFF 64 Kbytes Sector 48 to Page 768 to Sector 63 1024 0x08030000-0×0803FFFF 64 Kbytes 10/50 Doc D 16024 ReV 5

试读 50P STM32L151xx,STM32L152xx和STM32L162xx的Flash和EEPROM的编程手册.pdf
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zdfdy 有点用,可惜是英文的
我姓梁 谢谢分享,刚好用上
mylove_2009 有点帮助,还可以吧
sfxd123 谢谢分享,还没看呢,不智能用上不。
josh915 使用eeprom写0的时候居然死机了,查查原因
liuchengyi521 谢谢分享。对我有帮助。
Tmx999 ST主站没有,这里居然有。
lanfengzyz 正好用上,谢谢!
康小玲 资料非常好 非常有用 赞一个
zuichudehuanghun 太实用了,赞赞、、
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