Printed Circuit Board Design Techniques for EMC Compliance 2nd edition

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Printed Circuit Board Design Techniques for EMC Compliance
PRINTED CIRCUIT BOARD DESIGN TECHNIQUES FOR EMC COMPLIANCE A Handbook for Designers Second Edition Mark I. Montrose Montrose Compliance Services, Inc IEEE Electromagnetic Compatibility Society, Sponsor ◆ IEEE PRESS IEEE Press Series on ele ectronics lechnology Robert Herrick, Series editor The Institute of Electrical and Electronics Engineers, Inc, New York This book may be purchased at a discount from the publisher when ordered in bulk quantities. Contact IEEE Press Marketing Attn: Special Sales 445 Hoes Lane P O. Box 1331 Piscataway, NJ 08855-1331 Fax:+17329819334 For more information about IEEE Press products, visit the TeEeOnlineCatalog&storE:http://www.ieee.org/ieeestore o 2000 by the Institute of Electrical and Electronics Engineers, Inc 3 Park Avenue 17 Floor New york, NY 10016-5997 All rights reserved. No part of this book may be reproduced in any form, nor may it be stored in a retrieval system or transmitted in any form, without written permission from the publisher. Printed in the United States of America 10987654321 ISBN0-7803-53765 HEEE Order No. PC5816 Library of Congress Cataloging-in-Publication Data Montrose, Mark I Printed circuit board design techniques for EMC compliance: a handbook for designers Mark I Montrose.--2nd ed p cm.(EEE Press series on electronics technology) "IEEE Electromagnetic Compatibility Society, sponsor Includes bibliographical references and index ISBN0-7803-5376-5 Printed circuits--Design and construction. 2. Electromagnetic compatibility. L.IEEE Electromagnetic Compatibility Society. IL. Title. Il Series TK7868P7M662000 00-021088 To my Family Margaret Maralena, and Matthew Contents Preface xiii Acknowledgments xix List of Figures xxi List of Tables xxv CHAPTER 1 Introduction 1 1.1 Fundamental definitions 1 1.2 Elements of the Electromagnetic Environment 2 1.3 Nature of interference 4 1.4 Regulatory Requirements--North America 5 1.5 Regulatory Requirements-Worldwide 6 1.6 Standards 7 1.6.1 Basic Standards 7 1. 6.2 Generic Standards 8 1.6.3 Product Family standards 8 1.6.4 Classification of TE Products 9 1.7 Emission Requirements 9 1.8 Immunity Requirements 10 1. 9 Additional Regulatory Requirements-North America 11 1.10 Supplemental Information 11 References 12 Contents CHAPTER 2 Printed Circuit Board Basics 13 2.1 Hidden RF Characteristic of Passive Components 14 2.2 How and Why RF Energy Is Developed Within the PCB 15 2.3 Magnetic Flux and Cancellation Requirements 18 2.4 Routing Topology Configurations 19 2.4.1 Microstrip 19 2.4.2 Stripline 19 2.5 Layer Stackup Assignment 21 5.1 Single-Sided Assembly 22 2.5.2 Double-Sided Assembly 24 2.5.3 Four-Layer Stackup 27 2.5.4 Six-Layer Stackup 30 2.5.5 Eight-Layer Stackup 33 2.5.6 Ten -Layer Stackup 35 2.6 Radial Migration 39 2.7 Common-Mode and Differential-Mode currents 39 2.7.1 Differential-Mode Currents 40 2.7.2 Common-Mode Currents 4 2.8 RF Current Density Distribution 42 2.9 Grounding Methodologies 43 2.9.1 Single-Point Grounding 44 2.9.2 Multipoint Grounding 45 2.10 Ground and Signal Loops Excluding Eddy Currents)47 2. 11 Aspect Ratio-Distance Between Ground Connections 48 2.12 Image Planes 51 2.13 Slots Within an Image Plane 55 2.14 Functional Partitioning 57 2. 15 Critical Frequencies(20)59 2.16 Logic Families 60 2.16.1 Edge Rate Transitions 61 References 60 CHAPTER 3 Bypassing and Decoupling 65 3.1 Review of Resonance 66 3.1.1 Series Resonance 67 3.1.2 Parallel Resonance 67 3.1.3 Parallel C-Series RL Resonance(Antiresonant Circuit)68 3.2 Physical Characteristics 68 3.2.1 Impedance 68 3.2.2 Capacitor Types 69 3.2.3 Energy Storage 69 3.2.4 Resonance 71 3.3 Capacitors in Parallel 75 3.4 Power and ground Planes 76 3.4.1 Calculating Power and Ground Plane Capacitance 77 Contents IX 3.4.2 Combined Effects of Planar and Discrete Capacitors 79 3.4.3 Buried Capacitance 79 3.5 Placement 81 3.5.1 Power Pianes 81 3.5.2 Equivalent Circuit Model of a PCB 82 3.5.3 Decoupling Capacitors 82 3. 5. 4 Single- and Double-Sided Assemblies 86 3.5.5 Mounting Pads 86 3.5.6 Microvias 88 3.6 How to Properly Select a Capacitor 89 3.6.1 Bypass and Decoupling 89 3.6.2 Capacitive Effects on Signal Traces 91 36.3Buk94 References 96 CHAPTER 4 Clock Circuits, Trace Routing, and Terminations 99 4.1 Creating Transmission Lines Within a PCB 99 4.2 Topology Configurations 101 4.2.1 Microstrip Topology 101 4.2.2 Embedded Microstrip Topology 102 4. 2. 3 Single-Stripline Topology 104 4.2. 4 Dual or Asymmetric Stripline Topology 105 4.3 Propagation Delay and Dielectric Constant 11 O 4.2.5 Differential Microstrip and stripline Topology 1 4.4 Capacitive Loading of Signal Traces 112 4.5 Component Placement 114 4.6 Impedance Matching-Reflections and Ringing 116 4.7 Calculating Trace Lengths(Electrically Long Traces)117 4. 8 Trace Routing 122 4. 8. 1 Single-Ended Transmission Lines 122 4.8.2 Differential Pair Signaling 124 4. 9 Routing Layers 126 4.9. 1 Which Layers to route traces on 126 4.9.2 Layer Jumping Use of vias 129 4.10 Crosstalk 131 4.10.1 Description of Crosstalk 13 4.10.2 Design Techniques to Prevent Crosstalk 134 4. 1 1 Trace Separation and the 3-W Rule 136 4.12 Guard/ shunt traces 137 4.13 Trace Termination 141 4.13.1 Series Termination 143 4.13.2 End Termination 144 4.13.3 Parallel Termination 145 4.13. 4 Thevenin Network 145 4.13.5 AC Network 147 4.13.6 Diode Network 147 Contents 4.13.7 Differential or Paired Signaling 149 References 150 CHAPTER 5 Interconnects and 9o 151 5.1 Partitioning 152 5.1.1 Functional Subsystems 152 5.1.2 Quiet Areas 152 5.1.3 Internal Radiated Noise Coupling 153 5.2 isolation and Partitioning( Moating)154 5.2.1 Method 1: Moating 155 5.2.2 Method 2: Bridging in a Moat-Partitioning 157 5.3 Filtering and grounding 159 5.3.1 Filtering 159 5.3.2 Why l /0 Cables and Interconnects Radiate 162 5. 3. 3 Grounding(I/O Connector)163 5.4 Local Area Network 1/0 Layout 164 5.5 Video 167 5.6 Audio 171 References 173 CHAPTER 6 Electrostatic Discharge Protection 175 6.1 Introduction 175 6.2 Triboelectric Series 176 6.3 Failure Modes from an ESD Event 176 6.4 Design Techniques for ESd Protection 180 6.4.1 Single- and Double-Sided PCBS 181 6.4.2 Multilayer PCBS 183 6.5 Guard Band Implementation 188 References 190 CHAPTER 7 Backplanes, Ribbon Cables, and Daughter Cards 193 7.1 Basics 193 7.2 Connector Pinout Assignment 194 7. 3 AC Chassis Planes 195 7. 4 Backplane Construction 195 7.5 interconnects 200 7.6 Mechanical 202 7.7 Signal Routing 203 7.8 Trace Length/Signal Termination 203 7. 9 Crosstalk 204 7.10 Ground Loop Control 207 7.11 Ground Slots in Backplanes 207 References 209

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试读 127P Printed Circuit Board Design Techniques for EMC Compliance 2nd edition
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2014-06-03
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