Cyclone II Device Handbook.pdf

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Cyclone II Device Handbook
A吉RA Contents Chapter Revision Dates ■1D■■■■■1■D■■■■■ XI About this handbook XI How to Contact altera Typographic Conventions……… Section I. Cyclone ll Device Family Data Sheet Revision history Chapter 1 Introduction Introduction Low-Cost Embedded Processing Solutions Low-Cost DSP Solutions Refe Document revision history Chapter 2. Cyclone Il Architecture Functional Description...... Logic elements…… LE Operating Modes Logic Array Blocks LAB Interconnects LAB Control signals Multitrack Interconnect Row Inte Column Interconnects Device routing... Global Clock Network Phase-Locked Loops …2-16 Dedicated clock pins 2-20 Dual-Purpose Clock pins .2-20 Global Clock Network Global Clock network distribution 2-23 PLLs Embedded Memory Memory modes ... Clock modes 2-31 M4 K Routing Interface……… 2-31 Altera Corporation Contents Embedded multipliers 2-32 Multi P Embedded Multiplier routing Interface 236 I/O Structure features.. External Memory Interfacing 2-44 Programmable Drive Strength 2-49 en in Output 2-50 Slew rate control Bus hold 2-51 Programmable Pull-Cp Resistor 2-51 Advanced I/O Standard Support 2-52 High-Speed Differential Interfaces 253 Series On-Chip Termination I/O Banks Multi Volt I/o Interface Chapter 3. Configuration Testing IEEE Std 1149.1 (TAG) Boundary Scan Support Configuration…… Operating modes 3 Configuration Schemes Cyclone ii automated single event upset detection Custom-Built Circuitry Software interface Document Revision history Chapter 4. Hot Socketing& Power-On Reset Introduction Devices Can Be Driven before Power-Up I/ O Pins Remain Tri-Stated during Power-Up……… 4-2 Hot-Socketing Feature Implementation in Cyclone ll devices Power-On Reset Circuitry ake-up" Time for CycloneⅡ Devices………… …-5 Document revision history 4-7 Chapter 5. DC Characteristics and Timing Specifications Operating Conditions Single-Ended I/O Standards Differential I/O Standards DC Characteristics for Different Pin Types On-Chip Termination Specifications Power Consumption Timing Specifications…… 5-14 Preliminary and Final Timing Specifications 5-14 Performance…… 15 Altera Corporation Cyclone ll Device Handbook, volume 1 Contents Internal Timing…… Cyclone ii clock Timing parameters Clock Network skew Adders .529 IOE Programmable delay Default Capacitive Loading of Different I/O Standards 5-31 I/O Delays Maximum Input and Output Clock rate 5-46 High Speed i/o Timing specifications External memory Interface specifications 5-63 JTAG Timing Specifications……… PLL Timing specifications Duty cycle distortion DCD Measurement techniques Referenced documents Document revision history Chapter 6. Reference Ordering Information Software Device Pin-Outs Ordering Information 6-1 Document revision history Section l clock Management Revision history 着“·上 Chapter 7. Plls in cyclone ll devices Introduction Cyclone Ii Pll hardware Overview PLL Reference Clock generation Clock Feedback modes… ,7-10 Normal mode…… 7-10 Zero delay buffer mode 7-11 Source-Synchronous Mode :““-““ 7-13 Hardware Features 7-14 Clock multiplication division Programmable duty cycle .7-15 Phase-Shifting Implementation 7-16 Control signals…7-17 Manual clock switchover 7-20 Clockin 7-21 Global Clock network 7-21 Clock control block .7-24 lobal Clock network clock source generation .7-26 Global Clock network power down 7-28 Altera Corporation Cyclone ll Device Handbook, Volume Contents 7-29 Board layout… vcca &x gNDa ...731 vccd GnD Section Il Memory Revision history 了 Chapter 8. Cyclone l Memory Blocks Introduction Control signals Parity Bit Support…………… Byte Enable support 8-4 Packed Mode Support… Address clock enable 8-6 Memory modes Single-Port mode Simple Dual-Port Mode True Dual-Port mode 8-12 Shift register mode ROM MOde 8-16 FIFO Buffer mode ....................................................................................................8-16 Clock modes 16 Independent Clock Mode Input/Output Clock Mode 19 Read/write Clock mode Single-Clock mode Power-Up Conditions memory Initialization Read-During- Write Operation at the Same address Same-Port Read-During-Write Mode 8-28 Mixed-Port Read-During-Write mode 8-29 Conclusion 8-30 Referenced documents 8-30 Chapter 9. External Memory Interlaces Introduction External Memory Interface Standards 9-2 DDR&DDR2 SDRAM…… QDRII SRAM Cyclone II DDr Memory Support overview Data Data strobe pins 9-10 Clock. Command address pins 9-14 Parity dm ECc pins .9-14 Altera Corporation Cyclone ll Device Handbook, volume 1 Contents Phase lock loop(PLL)……..… 9-15 Clock delay control 9-15 DQS Postamble .916 DDR Input registers… .9-18 DDR Output Registers 9-21 Bidirectional DDR Registers 9-2 Conclusion 9-24 Document Revision history Section V 10 Standards Revision history Chapter 10. Selectable Iy0 Standards in Cyclone lI Devices Introduction…… 10-1 Supported i/o standards 33 V LVTTL(EIA/ JEDEC Standard EsD8-B)…… 10-3 3.3-V LVCMOS(EIA/JEDEC Standard JESD8-B) 10-4 3.3-V(PCI Special Interest Group [SIG] PCI Local Bus Specification Revision 3.0) 10-4 3.3-V PCI-X 10-6 Easy-to-Use, Low-Cost PCI Express solution 2.5-V LVTTL (EIA/JEDEC Standard EIA/ JESD8-5 10-7 2.5-V LVCMOS(EIA/JEDEC Standard EIA/JESD8-5 …10-7 SSTL-2 Class I and II(EIA/JEDEC Standard JESDS-9A) .10-7 Pseudo-Differential SSTL-2 ...………108 1.8-V LVTTL (EIA/JEDEC Standard ElA/JESD8-7) 10-9 1.8-V LVCMOS (EIA/JEDEC Standard EIA/ JESD8-7) .10-10 sTL-18 Class i and II .10-10 1. 8-V HStL Class i and ii Pseudo-Differential SSTL-18 Class i and Differential SsfL-18 Class ll 10-12 1.8-V Pseudo-Differential HSTL Class i and II 10-13 1.5-V LVCMOS (EIA/JEDEC Standard JESD8-11) 10-1 1.5-V HSTL Class i and il 10-14 15-Ⅴ Pseudo- Differential hstl class i and ii…… 10-15 LVDS, RSDS and mini-LVDS 10-16 Differential LVPECL 10-17 cloneⅡI/ O Banks…… 10-18 Programmable Current Drive Strength 10-24 Voltage-Referenced l/o standard Termination Differential I/o Standard Termination 10-26 I/O Driver Impedance Matching(Rs)and Series Termination(rs) …10-27 Pad Placement and dc guidelines 10-27 Differential Pad placement Guidelines 10-28 VREE Pad Placement guidelines 10-29 DC Guidelines.… 0-32 5.0-V Device Compatibility 10-34 Altera Corporation Cyclone ll Device Handbook, Volume Contents Refe 10-37 Referenced Documents Document Revision history 10-38 Chapter 11. High-Speed Differential Interfaces in Cyclone ll Devices Introduction Cyclone li high-Speed I/O Bank 11-1 Cyclone II High- Speed I/ O Interface…… I/O Standards Support .... LVDS Standard Support in Cyclone II Devices RSDS I/O Standard Support in Cyclone II Devices 11-7 mini-LVDS Standard Support in Cyclone ll devices....... 11-9 L. VPECI Support in Cyclone II l1-1 Differential SsfL Support in Cyclone ll Devices 11-12 Differential hstl Support in Cyclone lI devices 11-13 High-Speed I/O Timing in Cyclone II Devices 11-14 Design guidelines 11-16 Differential Pad placement guidelines Board Design Considerations 11-16 Conclusion 11-17 Section v. dsp Revision history 11-1 Chapter 12. embedded multipliers in cyclone ll devices Introduction Embedded multiplier block Overview ..... 12-2 Architecture Input Registers Multiplier Stage………… Output Registers s上 Operational mod 18-Bit Multipliers 9- Bit multipliers… Software Support…… Conclusion Section VI. Configuration Test Revision history Chapter 13. Configuring Cyclone l Devices Introduction 13-1 Altera Corporation Cyclone ll Device Handbook, volume 1 Contents Cyclone ll configuration Overview Configuration File Format Configuration data Compression 133 Active Serial Configuration(Serial Configuration Devices Single device As Configuration Multiple device As Configuration ... .13-12 Configuring Multiple Cyclone Il Devices with the Same Design………………………13-15 Estimating As Configuration Time 13-18 Programming Serial Configuration Devices 13-19 PS Configu 13-22 Single device PS Configuration Using a MaX lI Device as an External Host 13-22 Multiple Device PS Configuration Using a MAX II Device as an External Host 1326 PS Configuration Using a Microprocessor Single device PS Configuration Using a Configuration Device……… 13-32 Multiple device ps configuration using a Configuration device..............13-37 PS Configuration USing d cable 13-48 jTAG Configuration 13-53 Single de JTAG Configuration JTAG Configuration of Multiple devices…… 1360 Configuring Cyclone II FPGAs with Runner ∴41360 Combining TAg& Active Serial Configuration Schemes 13-61 Programming Serial Configuration Devices In-System Using the jTAG Interface Device Configuration Pins 13-64 Conclusion 13-70 Chapter 14. IEEE 1149. 1(JTAG)Boundary-Scan Testing for Cyclone ll Devices Introduction IEEE Std. 1149.1 BST Architecture 14-2 IEEE Std 1149.1 Boundary-Scan Register ,着由·“上 44 Boundary-Scan Cells of a Cyclone II Device I/OPin…… 14-4 IFEF Std 1149.1 BST Operation Control 14-6 SAMPLE/PRELOAD Instruction Mode 14-9 Capture Phase .14-10 Shift Update Phases 14-10 EXTEST Instruction mode 14-11 Capture Phase 14-12 Shift update phases 14-12 BYPASS Instruction mode 14-13 IDCODE Instruction mode 1414 USERCODE Instruction Mode 14-14 CLAMP Instruction mode 14-14 HIGHZ Instruction mode .14-15 I/O Voltage Support in jTAG Chai 1415 Using IEEE Std 1149.1 BST Circuitry ;a; 14-16 BST for Configured Devices 14-17 Disabling ieee std 1149.1 BST Circuitry 14-18 Altera Corporation Cyclone ll Device Handbook, Volume Contents Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing 14-18 oundary-Scan Description Language(BSDly Support 14-19 鲁·上 1419 References Document Revision history 14-20 Section VI. PCB Layout Guidelines Revision history Chapter 15. Package Information for cyclone ll Devices Introduction Thermal resistance… 15-2 Package Outlines 144-Pin Plastic Thin Quad Flat Pack(TQFP)-Wirebond 15-4 208-Pin Plastic Quad Flat Pack(PQFP)-Wirebond 15-7 240-Pin Plastic Quad Flat Pack(PQFP) 256-Pin FineLine Ball-Grid Array, Option 2-Wirebond 15-1 484-Pin FineLine BGA, Option 3 rebond 15-13 484-Pin ultra fine line bga- wirebond 15-15 672-Pin Fineline bGa Package, Option 3- Wirebond 896-Pin FineLine BGA Package -Wirebond 15-19 Altera Corporation Cyclone ll Device Handbook, volume 1

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