Samsung KLM4G1FETE-B041(eMMC5.1 32Gb based)1.0 datasheet
SAMSUNG CONFIDENTIAL Rev. 1.0 KLMAG1FETE-B041 datasheet eMMc Table of contents 10 PRODUCT LIST 4 2.0 KEY FEATURES 30 PACKAGE CONFIGURATIONS 3. 1 153 Ball Pin Configuration 3.1.1 11mm x 10mm x 0.8mm Package Dimension 2 Product Architecture 40HS400 mode 5.0 New eMMC51 Features 5.1 Overview 5.2 Command Queuing 5.2.1 CMD Set Description 5.2.2 New Response: QSR(Queue Status Register) 5.2.3 Send status. CMD13 5.2.4 Mechanism of CMD Queue operation 525 CMD Queue Register description…… 9999990000 3 Enhanced strobe mode 4 RPMB Throughput improve…… 5.5 Secure Write Protection 11 6.0 Technical notes 6. 1 S/ Algorithm 12 6.1.1 Partition Management 12 6.1.11 Enhanced partition(Area)…… .12 6.1.2 Boot operation 6.1.3 User Density 6.1.4 Auto Power Saving Mode 6.1.5 Performance 14 70 REGISTER VALUE 15 7.1 OCR Register……… 15 7.2 CID Register 15 7. 2. 1 Product name table(In CID Register) 15 7.3 CSD Register 7. 4 Extended CSD Register............ 17 80 AC PARAMETER 21 8. 1 Timing Parameter 21 8.2 Previous Bus Timing Parameters for DDR52 and HS200 mode are defined by JEDEC standard 8.3 Bus Timing Specification in HS400 mode 2 8.3.1 HS400 Device Input Timing 2 8.3.2 HS400 Device Output Timing 8. 4 Bus signal levels 24 8.4.1 Open-drain mode bus signal level 8. 4.2 Push-pull mode bus signal level eMMC 24 9.0 DC PARAMETER 9.1 Active Power Consumption during operation 9. 2 Standby Power Consumption in auto power saving mode and standby state 3 Sleep Power Consumption in Sleep state 25 4 Supply voltage 25 9.5 Bus signal line load IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS SAMSUNG SAMSUNG CONFIDENTIAL Rev. 1.0 KLMAG1FETE-B041 datasheet eMMc INTRODUCTION SAMSUNG eMMC is an embedded MMc solution designed in a BGa package form eMMC operation is identical to a MMc device and therefore is a sim- ple read and write to memory using MMC protocol v5. 1 which is a industry standard eMMC consists of NAND flash and a MMC controller 3V supply voltage is required for the nand area ( VDD or Vcc)whereas 1.8V or 3V dual supply voltage (VpD or Vcca) is supported for the MMC controller. SAMSUNG eMMC supports HS400 in order to improve sequential bandwidth, especially sequential read performance There are several advantages of using eMMC. It is easy to use as the MMc interface allows easy integration with any microprocessor with MMc host Any revision or amendment of NANd is invisible to the host as the embedded MMc controller insulates NAND technology from the host. This leads to faster product development as well as faster times to market The embedded flash management software or FTL(Flash Transition Layer ) of eMMC manages Wear Leveling Bad Block Management and ECC.The FTL supports all features of the Samsung NAND flash and achieves optimal performance 10 PRODUCT LIST [Table 1] Product List Capacities eMMc Part d NAND Flash Type User Density (% Power System Package size Pin Configuration Interface power VDD(170-1.95Vor 4 GBKLM4G1FETE-B041 32Gbx 1 2.7-3.6V 1 mmx 10mm x0. 8 153FBGA VDDF (2.7V-36V) 2.0 KEY FEATURES embedded MultiMediacard ver. 5. 1 compatible SAMSUNG eMMC supports features of eMMC5 1 which are defined in JEDEC Standard Major Supported Features: HS400, Field Firmware Update, Cache, Command Queuing, Enhanced Strobe Mode Secure Write Protection, Partition types Non-supported Features: Large Sector Size(4KB) Backward compatibility with previous MultiMediaCard system specification(1bit data bus, multi-eMMC systems) Data bus width 1bit(Default), 4bit and 8bit MMC IF Clock Frequency: 0-200MHz MMC I/F Boot Frequency 0-52MHz Temperature: Operation (-25C-85C), Storage without operation(-40C-85c) Power Intertace power-VccQ(1.70V-195V or 2.7V-36V), Memory power- Vcc(2.7V-36v) IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS SAMSUNG SAMSUNG CONFIDENTIAL Rev. 1.0 KLMAG1FETE-B041 datasheet eMMc 30 PACKAGE CONFIGURATIONS 3.1 153 Ball Pin Configuration [Table 2]153 Ball Information Pin no Name D ATO DAT1 Ball-side down view ○ DAT2 B2 DaT B3 DATa B4 DAT5 DAT DAT K5 RSTN 5678910 A()○) B○四四她四的○O○○○○○ M4 c○@○@○@○○○○○○○○ N4 CCQ D○○○○ CCQ E○○○( 88 G F5 J10 Ncc H○○○ K9 VDDI K M5 CMD ○○○ H5 Data strobe M○○○@@@○○○○○○○○ M6 CLK N○四○@c○○○○○○○○○ J5 SS P○○@c③○○○@○○○○ A6 SS C4 G5 H10 SS V SS SS P4 Vss Figure 1.153-FBGA ●CLK: Clock input Data Strobe: Data Strobe is generated from eMMc to host In HS400 mode, read data and crc response are synchronized with Data Strobe CMD: a bidirectional signal used for device initialization and command transfers Command operates in two modes, open-drain for initialization and push-pull for fast command transfer DATO-7: Bidirectional data channels. It operates in push-pull mode rst n Vcc: Supply voltage for flash memory VccQ: Supply voltage for memory controller VDDi: Internal power node to stabilize regulator output to controller core logics Vss: Ground connections RFU: Reserved for future use, do not use for any usage IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS 5 SAMSUNG SAMSUNG CONFIDENTIAL Rev. 1.0 KLMAG1FETE-B041 datasheet eMMc 3.1.1 11mm x 10mm x 0.8mm Package Dimension #A1 INDEX MARK 11.000.10 05013=650 囚 11.00C.10 0.08 MAX 0.50 141211198765432 #A1 A (Datum B) OOOOOOOOOOOOOO OOOO ○ O OOOOOo OOC O OO o OOO ○O O○O OOO OOOOOO O0O M N OOOOOOOJOOOOOOE 0.22±0.05 0.7010.10 atum a 153-00.300.05 TOP VIEW 0150A回 BOTTOM VIEW Figure 2. 11mm x 10mm x 0.8mm Package Dimension IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS -6 SAMSUNG SAMSUNG CONFIDENTIAL Rev. 1.0 KLM4G1FETE-B041 datasheet eMMc 3.2 Product Architecture eMMC consists of NAND Flash and Controller. Vcco is for Controller power and Vcc is for flash power V RESET t Core Regulator s control Signal Memory uDDI Block DAT[7:0] MMC Controller Figure 3. eMMC Block Diagram IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS SAMSUNG SAMSUNG CONFIDENTIAL Rev. 1.0 KLMAG1FETE-B041 datasheet eMMc 40 HS400 mode eMMC50 product supports high speed DDR interface timing mode up to 400MB/s at 200MHz with 1.8V/O supply HS400 mode supports the following features DDR Data sampling method CLK frequency up to 200MHz DDR(up to 400Mbps) Only 8-bits bus width available signaling levels of 1. 8V SiX selectable Drive Strength(reter to the table below) lable 3]170 driver strength types Driver Type HS200&HS400 Nominal Impedance Approximated driving Remark capability compared to Type-0 0 50 x1 ult Driver Type e Supports up to 200MHz operation Optional 339 1.5 Supports up to 200MHz Operation Optional 66 x0.75 tThe weakest driver that supports up to 200MHz operation. For low noise and low emi systems 3 Optional 1009 x05 laximal operating frequency is decided by Host design Optional 40 x1.2 Supports up to 200MHz DDR operation NOTE: 1)Support of Driver Type-0 is default for HS200 HS400 Device, while supporting Driver types 1-4 are optional for HS200& HS400 Device [Table 4] Device type values(EXT_ CSD register: DEVICE_ TYPE [196]) Bit Device Type Supportability 7 HS400 Dual Data Rate eMMC 200 MHz-12V 1/O Not support HS400 Dual Data Rate eMMC Q 200 MHz-18V l/O ort 5 HS200 Single Data Rate eMMC 200 MHz -1.2V1/O Not support 4 HS200 Single Data Rate eMMC 200 MHz -18V 1O Support High-speed Dual Data Rate eMMC @52MHz -1.2VIO Not support High-Speed Dual Data Rate eMMC 52MHz-18V or 3V10 Support High-Speed eMMC@ 52MHz-at rated device voltage(s) rt 0 High-Speed eMMC 26MHz-at rated device voltage(s) Support [Table 5] Extended CSD revisions(EXT CSD register: EXT_ CSD_ REV[192]) Value Timing Interface EXT CSD Register Value 255-8 Reserved 8 Revision 1.8(for MMC V5. 1) 0x08 7 Revision 1.7(for MMCV5.0) Revision 1.6 (for MMC V4.5, V4.51) 5 Revision 1.5(for MMC V4.41) Revision14(○ bolete) Revision 1.3 (for MMC V4. 3) 2 Revision 1.2(for MMC V4.2) Revision 1.1(for MMC V4.1) 0 Revision 1.0 (for MMC V4.0) [Table 6] High speed timing values(EXT CSD register: HS TIMING [185) Value Timing Interface Supportability 0x0 Selecting backwards compatibil ity interface timing Support High Speed Support 0x2 HS200 Support 0×3 HS400 S rt IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS -8 SAMSUNG SAMSUNG CONFIDENTIAL Rev. 1.0 KLMAG1FETE-B041 datasheet eMMc 5.0 New eMMC5 1 Features 5.1 Overview New Feature JEDEC Support Cache Flushing Report Mandatory Background operation control Mandatory Yes Command Queuing Optional Ye Enhanced strobe Optional Yes RPMB Throughput improve Optional Yes Secure Write Protection Optional Yes 5.2 Command Queuing To facilitate command queuing in eMMC, the device manages an internal task queue that the host can queue during data transfer tasks Every task is issued by the host and initially queued as pending. The device works to prepare pending tasks for execution. When a task is ready far exe- cution, its state changes to read execution The host tracks the state of all queued tasks and may order the execution of any task, marked as"ready for execution, by sending a command indicating its task ID. The device executes the data transfer transaction after receiving the execute command(cMD46/CMD47) 5.2.1 CMD Set Description [Table 7] CMD Set Description and Details CMD Type Argument Abbreviation Purpose [31] Reliable Write Request [30] DAT DIR-""write/"1 read [29] tag request CMD44 ac/R1[28: 25]context ID QUEUED TASK PARAMS Detine direction of operation(Read or Write)and [24]forced programming Set high priority CMD Queue with task ID [23] Priority: "0"simple/"1 high [20: 16 TASK ID [15: 0] number of blocks CMD45 ac/R1 [31: 0] Start block address QUEUED TASK ADDRESS Indicate data address for queued CMD CMD46 adtc/R1 [20: 16] TASK ID EXECUTE READ TASK (Read)Transmit the requested number of data blocks CMD47 adtc/R1 [20: 16] TASK ID EXECUTE WRITE TASK (Write)Transmit the requested number of data blocks :16 Task ID Reset a specific task or entire queue CMD48 ac/R1b 3: 0]TM op-code CMDQ TASK MGMT 20: 16] when TM op-code 2h these bits represent TaskID When TM op-code= lh these bits are reserved 5.2.2 New Response: QSR (Queue Status Register) The 32-bit Queue Status Register(QSR)carries the state of tasks in the queue at a specific point in time. The host has read access to this register through device response to SEND- STATUS command (CMD13 with bit[ 15]=1), RI's argument will be the 32-bit Queue Status Register(QSR). Every bit in the QSR represents the task who's id corresponds to the bit index. If bit Qsr[=0, then the queued task with a Task Id i is not ready for execution. The task may be queued and pending or the Task ID is unused. If bit QSRO=1, then the queued task with Task Id i is ready for execution 5.2.3 Send status: CMD13 CMD13 for reading the Queue Status Register(QSR)by the host. If bit[15] in CMD13's argument is set to 1, then the device shall send an R1 Response with the qsr instead of the Device Status. There is still legacy CMD13 with Response IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS 9 SAMSUNG SAMSUNG CONFIDENTIAL Rev. 1.0 KLMAG1FETE-B041 datasheet eMMc 5.2.4 Mechanism of CMD Queue operation Host issues CMD44 with Task ID number, Sector, Count, Direction, Priority to the device followed by CMD45 and host checks the Queue Status check with CMD13[15]bits to 1. After that host issues CMD46 for Read or CMD47 for write During CMD queue operation, CMD44/CMD45 is able to be issued at anytime when the cmd line is not in use *Read Execution 46‖R1 CMD 44R145R144‖R1‖45‖R113QsR 44R145‖R1 13 QSR 47R1 *Write Execl DATA Data Data 5.2.5 CMD Queue Register description Configuration and capability structures shall be added to the ExT CSD register, as described below T Table 8] CMD Queuing Support (EXT CSD register: CMDQ_ SUPPORT [308]) Bit7 Bit6 Bit5 Bit4 Bit 3 Bit2 Bit1 Bito Reserved CMD Queue supportability This field indicates whether the device supports command queuing or not OXD: CMD Queue function is not supported Ox1: CMD Queue function is supported TTable 9] Command Queue Mode Enable (EXT CSD register: CMDQ_MODE_EN [15]) Bit7 Bit6 Bit5 Bit4 Bit 3 Bit2 Bit1 Bito Reserved 0x00 This field is used by the host enable command queuing 0x0: Queue function is not enabled Ox1 Queue function is enabled [Table 10] CMD Queuing Depth (EXT CSD register: CMDQ DEPTH [307) Bit7 Bit6 Bit5 Bit4 Bit 3 Bit2 Bit1 Bito Reserved OXO This field is used to calculate the depth of the queue supported by the device Bit encoding [7: 5]: Reserved [4: 0]: N, a parameter used to calculate the Queue Depth of task queue in the device Queue depth= N+1 5.3 Enhanced strobe mode This product supports Enhanced Strobe in HS400 mode and refer to the details as described in eMMC5 1 JEDEC standard 5.4 RPMB Throughput improve [Table 11] Related parameter register in EXT CSD: WR REL PARAM[166 Name Field Bit Enhanced rPmb reliable write EN RPMB REL WR 4 R Bit[ 4]: EN_RPMB_ REL- WR(R) 0X0: RPMB transfer size is either 256B (single 512B frame)or 512B(Two 512B frame) 0 X1: RPMB transfer size is either 256B (single 512B frame), 512B(Two 512B frame), or 8KB(Thirthy two 512B frames) IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS SAMSUNG