LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY jiaotong IS
PORT (clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
R1,R2: OUT STD_LOGIC; --hong
Y1,Y2: OUT STD_LOGIC; --huang
G1,G2: OUT STD_LOGIC; --lv
dout7seg: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
sel: OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END ENTITY jiaotong;
ARCHITECTURE one OF jiaotong IS
SIGNAL count1: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL count2: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL cnt6: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL sec1,sec10,dir1,dir2,d1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL clk_1hz,clk_2hz,clk_10k: STD_LOGIC;
SIGNAL dir_flag: STD_LOGIC;
BEGIN
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (count1<16#F9F#) THEN
count1<=count1+1;
ELSE count1<=(OTHERS=>'0');
END IF;
END IF;
END PROCESS;
PROCESS(count1)
BEGIN
IF (count1<2000) THEN
clk_10k<='0';
ELSE clk_10k<='1';
END IF;
END PROCESS;
PROCESS(clk_10k)
BEGIN
IF (clk_10k'EVENT AND clk_10k='1') THEN
IF (count2<16#1387#) THEN
count2<=count2+1;
ELSE count2<=(OTHERS=>'0');
END IF;
END IF;
END PROCESS;
PROCESS(count2)
BEGIN
IF (count2<2500) THEN
clk_2hz<='0';
ELSE clk_2hz<='1';
END IF;
END PROCESS;
PROCESS(clk_2hz)
VARIABLE count : STD_LOGIC;
BEGIN
IF (clk_2hz'EVENT AND clk_2hz='1') THEN
count := NOT count;
IF count='1'THEN clk_1hz<='1';
ELSE clk_1hz<='0';