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RTL Design Style Guide

for Verilog HDL



Second Version

April 25, 2006



in a retrieval system. or transmitted in any form or by any means, mechanical, photocopying,

recording, or, otherwise without the prior written permission of the publisher, STARC

FFoorrwardward

ward

©©

Forward to the Second EditionForward to the Second Edition

The The RTL Design Style Guide, Second EditionRTL Design Style Guide, Second Edition, reflects the advances in design environments that, reflects the advances in design environments that

have been made since the 2003 publication of the first edition. The second edition introduces designhave been made since the 2003 publication of the first edition. The second edition introduces design

practices suitable for designs that are getting ever faster and larger. Major additions and changespractices suitable for designs that are getting ever faster and larger. Major additions and changes

are as follows:are as follows:

Added sectionsAdded sections

•Section 1.5.2, •Section 1.5.2, Consider metastable issues in signals between asynchronous clocksConsider metastable issues in signals between asynchronous clocks

•Section 1.5.4, •Section 1.5.4, Verifying the asynchronous interfaces between clock domains through RTLVerifying the asynchronous interfaces between clock domains through RTL

simulationsimulation

•Section 1.7.1, •Section 1.7.1, Considerations for using both ASICs and FPGAsConsiderations for using both ASICs and FPGAs

•Section 2.10.8, •Section 2.10.8, Division descriptionsDivision descriptions

•Section 3.4.4, •Section 3.4.4, Reducing power dissipation for RAM accessesReducing power dissipation for RAM accesses

•Section 3.5.9, •Section 3.5.9, Advanced CVS featuresAdvanced CVS features

•Section 3.5.11, •Section 3.5.11, Building a bug tracking systemBuilding a bug tracking system

•Section 4.5, •Section 4.5, Static timing analysisStatic timing analysis, was revised comprehensively. The following subsections were, was revised comprehensively. The following subsections were

added:added:

- Section 4.5.1, - Section 4.5.1, Timing analysis flow Timing analysis flow to Section 4.5.5,to Section 4.5.5, I/O ports and clock lines I/O ports and clock lines

•Section 5.2.1, •Section 5.2.1, Various clock definitionsVarious clock definitions

•Section 5.3.1.5, •Section 5.3.1.5, Removing net attributes and buffersRemoving net attributes and buffers

•Section 5.8, •Section 5.8, Translating dc_shell scripts to TclTranslating dc_shell scripts to Tcl

•Section 5.9, •Section 5.9, Commonly used Tcl commandsCommonly used Tcl commands

Modified chapters and sectionsModified chapters and sections

•Modified numeric limitations set forth in Chapter 1 such as gate counts to suit the current•Modified numeric limitations set forth in Chapter 1 such as gate counts to suit the current

situations.situations.

•Added figures and text to Section 1.4.4, •Added figures and text to Section 1.4.4, Multiple clock systemsMultiple clock systems

•Modified numeric limitations set forth in Chapter 2 such as the nesting level of the •Modified numeric limitations set forth in Chapter 2 such as the nesting level of the ifif statement, statement,

the number of items in the the number of items in the casecase statement, the number of states in a state machine and so on to statement, the number of states in a state machine and so on to

suit the current situations.suit the current situations.

•Modified text in Section 2.11, •Modified text in Section 2.11, State machine descriptionsState machine descriptions, to a more appropriate description., to a more appropriate description.

•Added a description of division and modulus to Section 3.2.5, •Added a description of division and modulus to Section 3.2.5, The function library of an arith-The function library of an arith-

metic operation improves data path design performancemetic operation improves data path design performance..

•Modified text in Section 3.3.6, •Modified text in Section 3.3.6, DFT in reset linesDFT in reset lines, to a more appropriate description., to a more appropriate description.

•Modified text in Section 3.5.8, •Modified text in Section 3.5.8, CVS basicsCVS basics, to a more appropriate description., to a more appropriate description.

•With the comprehensive revision of Section 4.5, •With the comprehensive revision of Section 4.5, Static timing analysisStatic timing analysis, added the following, added the following

subsections:subsections:

- Section 4.5.1, - Section 4.5.1, Timing analysis flowTiming analysis flow

- Section 4.5.2, - Section 4.5.2, Timing analysis in various operating modes and conditionsTiming analysis in various operating modes and conditions

•Modified the Design Compiler script language used in Appendix A-5 comprehensively from•Modified the Design Compiler script language used in Appendix A-5 comprehensively from

dc_shell to Tcl.dc_shell to Tcl.

•Reorganized the descriptions of advanced commands and logic synthesis strategies in Appendix A-•Reorganized the descriptions of advanced commands and logic synthesis strategies in Appendix A-

5 into Section 5.2, 5 into Section 5.2, Advanced dc_shell commandsAdvanced dc_shell commands, and Section 5.4, , and Section 5.4, General logic synthesisGeneral logic synthesis

strategystrategy..

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•Modified Section 5.7, •Modified Section 5.7, Comparisons between 2004.06 and earlier versionsComparisons between 2004.06 and earlier versions, with benchmark figures, with benchmark figures

using new versions of Design Compiler.using new versions of Design Compiler.

•Deleted the support status in RTL checkers (RTqualify and Verilint) and references to the related•Deleted the support status in RTL checkers (RTqualify and Verilint) and references to the related

sections in the sections in the Reuse Methodology Manual (RMM).Reuse Methodology Manual (RMM).

•Corrected several errors in the first edition and modified some descriptions to make them easier•Corrected several errors in the first edition and modified some descriptions to make them easier

to understand.to understand.

The The RTL Design Style GuideRTL Design Style Guide is organized into the following chapters: is organized into the following chapters:

Chapter 1, Chapter 1, Basic Design ConstraintsBasic Design Constraints, describes general design restrictions you should consider, describes general design restrictions you should consider

before you begin your design, such as naming conventions, design styles, clocking schemes, syn-before you begin your design, such as naming conventions, design styles, clocking schemes, syn-

chronous and asynchronous design considerations, hierarchical design philosophies, and so on.chronous and asynchronous design considerations, hierarchical design philosophies, and so on.

Chapter 2, Chapter 2, RTL Description TechniquesRTL Description Techniques, discusses basic RTL coding styles and techniques design-, discusses basic RTL coding styles and techniques design-

ers can apply to their designs. Also demonstrates coding styles for combinational and sequentialers can apply to their designs. Also demonstrates coding styles for combinational and sequential

logic, as well as how to use the logic, as well as how to use the alwaysalways,, function function, , ifif, , casecase and other statements. and other statements.

Chapter 3, Chapter 3, RTL Design MethodologyRTL Design Methodology, describes how to create function libraries, parameterize, describes how to create function libraries, parameterize

design resources, insert design-for-test (DFT) structures, implement low-power design techniques,design resources, insert design-for-test (DFT) structures, implement low-power design techniques,

manage design data and so on. Following the rules and recommendations set forth in this chaptermanage design data and so on. Following the rules and recommendations set forth in this chapter

improves reusability of your design resources.improves reusability of your design resources.

Chapter 4, Chapter 4, Verification TechniquesVerification Techniques, introduces simulation techniques, including how to parameter-, introduces simulation techniques, including how to parameter-

ize testbenches, how to use tasks, how to draw up a verification strategy, and so on.ize testbenches, how to use tasks, how to draw up a verification strategy, and so on.

Appendix A-5, Appendix A-5, Logic Synthesis Using Design CompilerLogic Synthesis Using Design Compiler, contains tips and hints for using logic, contains tips and hints for using logic

synthesis tools.synthesis tools.

The The RTL Design Style GuideRTL Design Style Guide contains five classes of material: contains five classes of material:

Specifies a mandatory design practice you Specifies a mandatory design practice you mustmust follow. follow.

DescriptionDescription

Specifies a design practice you Specifies a design practice you shouldshould follow. Even if you do not follow this recom- follow. Even if you do not follow this recom-

mendation, no problem will occur, provided an appropriate workaround is used.mendation, no problem will occur, provided an appropriate workaround is used.

Indicates preferred practice for designs, considering the design quality, codeIndicates preferred practice for designs, considering the design quality, code

readability and various tool limitations.readability and various tool limitations.

Indicates preferred practice for designs that does not need to be followed toIndicates preferred practice for designs that does not need to be followed to

the letter.the letter.

Provides a useful design tip or hint to keep in mind.Provides a useful design tip or hint to keep in mind.

ClassClass

SuggestionSuggestion

RReeccoommmmeennddaattiioonn 2 2

RReeccoommmmeennddaattiioonn 33

RuleRule

RRececoommmemennddaattiioonn 11

ContentsContents

Contents

©©

Table of ContentsTable of Contents

List of Items by LevelList of Items by Level............................................................................................................................................................................................................................................ List-1List-1

Chapter 1 Basic Design ConstraintsChapter 1 Basic Design Constraints....................................................................................................................................................................................................1-11-1

1.1.1.1. Naming conventionsNaming conventions ............................................................................................................................................................................................................................1-21-2

1.1.1.1.1.1. Basic naming conventionsBasic naming conventions ............................................................................................................................................................................................1-21-2

11..11.2..2. NNaammiing conventions of circuit and port names should be considered by the hierarchyng conventions of circuit and port names should be considered by the hierarchy1-61-6

1.1.3.1.1.3. Give meaningful names for signalsGive meaningful names for signals............................................................................................................................................................1-101-10

1.1.4.1.1.4. Naming conventions of Naming conventions of includeinclude file, file, parameter parameter and and `define `define (different from VHDL)(different from VHDL) ......1-121-12

1.1.5.1.1.5. Naming should consider clock systemsNaming should consider clock systems................................................................................................................................................1-141-14

1.2.1.2. Synchronous designSynchronous design ..........................................................................................................................................................................................................................1-161-16

1.2.1.1.2.1. Clock synchronous designClock synchronous design..........................................................................................................................................................................................1-161-16

1.3.1.3. Initial resetInitial reset......................................................................................................................................................................................................................................................1-181-18

1.3.1.1.3.1. Use asynchronous reset for initial resetUse asynchronous reset for initial reset..............................................................................................................................................1-181-18

1.3.2.1.3.2. Reset line hazardsReset line hazards..................................................................................................................................................................................................................1-231-23

1.3.3.1.3.3. Be careful about external noise on an initial reset signalBe careful about external noise on an initial reset signal........................................................................................1-241-24

1.4.1.4. ClocksClocks ......................................................................................................................................................................................................................................................................1-261-26

1.4.1.1.4.1. Creating modules for clock generation circuitsCreating modules for clock generation circuits........................................................................................................................1-261-26

1.4.2.1.4.2. Use clock tree synthesis for clock balancingUse clock tree synthesis for clock balancing................................................................................................................................1-281-28

1.4.3.1.4.3. Gated clocks should be used with special careGated clocks should be used with special care ..........................................................................................................................1-301-30

1.4.4.1.4.4. Multiple clock systemsMultiple clock systems ..................................................................................................................................................................................................1-321-32

1.5.1.5. Handling of asynchronous circuitsHandling of asynchronous circuits ............................................................................................................................................................................1-361-36

1.5.1.1.5.1. Consider metastable issues in signals between asynchronous clocksConsider metastable issues in signals between asynchronous clocks ..................................................1-361-36

1.5.2.1.5.2. Transferring data between asynchronous clock domainsTransferring data between asynchronous clock domains ........................................................................................1-411-41

1.5.1.5.33.. Use memory in transfers between asynchronous same-period clocksUse memory in transfers between asynchronous same-period clocks ..................................................1-451-45

1.5.1.5.44.. Verifying the asynchronous interfaces between clock domains throughVerifying the asynchronous interfaces between clock domains through

RTL simulationRTL simulation..........................................................................................................................................................................................................................1-461-46

1.5.5.1.5.5. Guaranteeing the setup/hold margin for synchronous RAMGuaranteeing the setup/hold margin for synchronous RAM ..............................................................................1-491-49

1.6.1.6. Hierarchical designHierarchical design............................................................................................................................................................................................................................1-511-51

1.6.1.1.6.1. Consider limitations based on hierarchical scaleConsider limitations based on hierarchical scale ..................................................................................................................1-511-51

1.6.2.1.6.2. Make basic blocks FF output & combinational circuit inputMake basic blocks FF output & combinational circuit input ............................................................................1-541-54

1.6.3.1.6.3. Follow sub-block (the levels below basic clocks) constraintsFollow sub-block (the levels below basic clocks) constraints................................................................................1-551-55

1.6.4.1.6.4. Do not insert gates into upper levels of basic blocksDo not insert gates into upper levels of basic blocks........................................................................................................1-571-57

1.6.5.1.6.5. Separate the data path section from the controllerSeparate the data path section from the controller............................................................................................................1-591-59

1.6.6.1.6.6. Designate buffer outputs in upper levels with 200,000 or more gatesDesignate buffer outputs in upper levels with 200,000 or more gates..................................................1-611-61

1.7.1.7. FPGAsFPGAs....................................................................................................................................................................................................................................................................1-631-63

1.7.1.1.7.1. Considerations for using both ASICs and FPGAsConsiderations for using both ASICs and FPGAs ................................................................................................................1-631-63

Chapter 2 RTL Description TechniquesChapter 2 RTL Description Techniques ........................................................................................................................................................................................2-12-1

2.1.2.1. Combinational logicCombinational logic................................................................................................................................................................................................................................2-22-2

2.1.1.2.1.1. Use Use always always constructsconstructs and and function function statements correctly (Verilog HDL only)statements correctly (Verilog HDL only)..........................2-22-2

2.1.2.2.1.2. Define combinational circuits using the Define combinational circuits using the functionfunction statement (Verilog HDL only) statement (Verilog HDL only) ..................2-52-5

2.1.3.2.1.3. In a In a function function statement, be careful to check arguments and bit widthstatement, be careful to check arguments and bit width ................................................2-72-7

2.1.4.2.1.4. Instructions for equation level descriptions (different from VHDL) Instructions for equation level descriptions (different from VHDL) ..........................................................2-92-9

2.1.5.2.1.5. Use a conditional operatorUse a conditional operator ((A)?B:C) ((A)?B:C) only once (Verilog HDL only)only once (Verilog HDL only) ........................................................2-122-12

Contents

Contents Contents

©©

2.1.6.2.1.6. Specifying the range of an arraySpecifying the range of an array ....................................................................................................................................................................2-142-14

2.2.2.2. always always construct description in combinational logicconstruct description in combinational logic......................................................................................................................2-162-16

2.2.1.2.2.1. Avoid the risk of generating latchesAvoid the risk of generating latches ..........................................................................................................................................................2-162-16

2.2.2.2.2.2. Define every input signal in an Define every input signal in an always always construct in the sensitivity listconstruct in the sensitivity list..........................................2-182-18

2.2.3.2.2.3. Initial value description in Initial value description in always always constructsconstructs (Verilog HDL only)(Verilog HDL only)............................................................2-202-20

2.3.2.3. FF inferencesFF inferences ..............................................................................................................................................................................................................................................2-242-24

2.3.1.2.3.1. Unify the description style of FF inferencesUnify the description style of FF inferences ................................................................................................................................2-242-24

2.3.2.2.3.2. Circuits will vary with non-blocking and blocking assignment statementsCircuits will vary with non-blocking and blocking assignment statements

(Verilog HDL only)(Verilog HDL only) ................................................................................................................................................................................................................2-292-29

2.3.3.2.3.3. Do not mix descriptions that have different edgesDo not mix descriptions that have different edges ..............................................................................................................2-312-31

2.3.4.2.3.4. Do not specify an initial FF value in a description Do not specify an initial FF value in a description (different from VHDL)(different from VHDL)..................................2-322-32

2.3.5.2.3.5. Do not use descriptions which generate FFs having fixed input valuesDo not use descriptions which generate FFs having fixed input values ..........................................2-332-33

2.3.6.2.3.6. Do not mix FF inferences with and without asynchronous resetsDo not mix FF inferences with and without asynchronous resets ............................................................2-342-34

2.4.2.4. Latch inferencesLatch inferences......................................................................................................................................................................................................................................2-372-37

2.4.1.2.4.1. Clearly distinguish a latch inference from a combinational circuitClearly distinguish a latch inference from a combinational circuit ........................................................2-372-37

2.5.2.5. Tri-state buffersTri-state buffers........................................................................................................................................................................................................................................2-402-40

2.5.1.2.5.1. Create modules for tri-state buffersCreate modules for tri-state buffers............................................................................................................................................................2-402-40

2.5.2.2.5.2. Consider high-impedance propagation in tri-state busesConsider high-impedance propagation in tri-state buses ..........................................................................................2-452-45

2.6.2.6. always always construct description that takes circuit structureconstruct description that takes circuit structure into accountinto account..........................................................2-462-46

2.6.1.2.6.1. Describe taking the circuit structure into accountDescribe taking the circuit structure into account............................................................................................................2-462-46

2.6.2.2.6.2. Avoid defining multiple output signals in a single Avoid defining multiple output signals in a single alwaysalways constructconstruct ....................................................2-492-49

2.7.2.7. if if statementsstatements ..............................................................................................................................................................................................................................................2-522-52

2.7.1.2.7.1. if if statements create prioritized circuitsstatements create prioritized circuits ..............................................................................................................................................2-522-52

2.7.2.2.7.2. Reduce conditional expressions of Reduce conditional expressions of if if statements with the same contentsstatements with the same contents........................................2-542-54

2.7.3.2.7.3. Decrease the number of Decrease the number of ifif statement nestsstatement nests ....................................................................................................................................2-572-57

2.7.4.2.7.4. Always surround multiple statements using Always surround multiple statements using blockblock statementsstatements

(begin-end) (Verilog HDL only)(begin-end) (Verilog HDL only) ..........................................................................................................................................................................2-592-59

2.8.2.8. casecase statements statements ........................................................................................................................................................................................................................................2-602-60

2.8.1.2.8.1. case case statements facilitate decoder/encoder descriptionstatements facilitate decoder/encoder description ................................................................................................2-602-60

2.8.2.2.8.2. Divide using Divide using ifif statement, etc. to avoid creating large tablesstatement, etc. to avoid creating large tables............................................................................2-632-63

2.8.3.2.8.3. Use Use default clausesdefault clauses .............................................................................................................................................................................................................. 2-652-65

2.8.4.2.8.4. Do not use complex Do not use complex casex casex statements (Verilog HDL only)statements (Verilog HDL only) ......................................................................................2-682-68

2.8.5.2.8.5. Expressions and case items in the Expressions and case items in the case case statement (Verilog HDL only)statement (Verilog HDL only)..............................................2-702-70

2.8.6.2.8.6. Beware of nesting in which Beware of nesting in which ifif statements and statements and casecase statements coexist statements coexist

(2.8.4 in the VHDL version)(2.8.4 in the VHDL version) ..................................................................................................................................................................................2-722-72

2.9.2.9. forfor statements statements ............................................................................................................................................................................................................................................2-742-74

2.9.1.2.9.1. Do not use Do not use forfor statements other than for simple repeating statementsstatements other than for simple repeating statements ............................................2-742-74

2.9.2.2.9.2. Limiting loop-variable operation in Limiting loop-variable operation in forfor statements statements............................................................................................................2-752-75

2.10.2.10. Operator and substitution descriptionsOperator and substitution descriptions ..............................................................................................................................................................2-772-77

2.10.1.2.10.1. Order of operators and assignment of 'x'Order of operators and assignment of 'x'............................................................................................................................................2-772-77

2.10.2.2.10.2. Efficient description using logical operational expressions (Verilog HDL only)Efficient description using logical operational expressions (Verilog HDL only)......................2-812-81

2.10.3.2.10.3. Match the bit width of the left side and the right side (Verilog HDL only)Match the bit width of the left side and the right side (Verilog HDL only) ..................................2-822-82

2.10.4.2.10.4. Take note of the different data types between the left and right sidesTake note of the different data types between the left and right sides

2.10.5.2.10.5. Do not share resources in speed critical circuitsDo not share resources in speed critical circuits....................................................................................................................2-872-87

2.10.6.2.10.6. Notes on arithmetic operationsNotes on arithmetic operations ........................................................................................................................................................................2-892-89

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