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xilinx A7xi系列数据手册 评分:

xilinx公司 A7系列FPGA数据手册。Artix®-7 FPGAs are available in -3, -2, -1, -1LI, and -2L speed grades, with -3 having the highest performance. The Artix-7 FPGAs predominantly operate at a 1.0V core voltage。
&A XILINX Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 2: Recommended Operating Conditions(1)(2)(Cont'd) Symbol escription MinTy Max Units REFP Externally supplied reference voltage 120125 1.30 Temperature Junction temperature operating range for commercial(C)temperature devices 0 85 Junction temperature operating range for extended(e)temperature devices 0 100 CCc Junction temperature operating range for industrial ( temperature devices -40 100 Junction temperature operating range for expanded (Q)temperature devices-40 125 Junction temperature operating range for military (M)temperature devices-55- 125 oC Notes 1. All voltages are relative to ground 2. For the design of the power distribution system consult 7 Series FPGAs PCB Design and Pin Planning Guide(UG483 3. If VcciN and VCcBRAM are operating at the same voltage, VcciNT and VccBRam should be connected to the same supply 4. Configuration data is retained even if Vcco drops to OV 5. Includes Vcco of 1. 2V, 1. 35V, 1.5V, 1.8V, 2.5v, and 3.3V at +5% 6. The lower absolute voltage specification always applies 7. See Table 9 for TMDS_33 specifications 8. A total of 200 mA per bank should not be exceeded 9. VccBATT iS required only when using bitstream encryption. If battery is not used, connect VcceaTT to either ground or VccAUX 10. Each voltage listed requires the filter circuit described in 7 Series FPGAs GTP Transceiver User Guide(UG482 Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ(1)MaxUnits DRINT Data retention VcciNT VOltage(below which configuration data might be lost) 0.75 DRI Data retention Vccaux Voltage(below which configuration data might be lost) REF REF leakage current per pin 15 HA Input or output leakage current per pin(sample-tested 15 A C1N(2 Die input capacitance at the pad 8 pF Pad pull-up(when selected)@VIN=OV, Vcco=3. 3V 90 330 A Pad pull-up(when selected)@ VIN=OV, VcCo =2.5V 68 250 A lRt Pad pull-up(when selected)@ ViN=OV, Vcco= 1.8V 220 HA Pad pull-up(when selected)@ VIn=oV, Vcco=1.5V 150 A Pad pull-up(when selected)@ Vin=oV, Vcco=1.2V 12 120 A RPD Pad pull-down(when selected)@ Vin=3.3V 68 330 A CCADC Analog supply current, analog circuits in powered up state 25 mA BATT ) Battery supply current 150 A Thevenin equivalent resistance ot programmable input termination to Vcco/2 28 (UNTUNED_SPLIT_40) RIN_TERM(4) Thevenin equivalent resistance of programmable input termination to Vcco/2 (UNTUNED_SPLIT_50) hevenin equivalent resistance of programmable input termination to Vcco/2 44 83 (UNTUNED_SPLIT_60) DS181(v124)Aprl4,2018 www.xilinx.com Product Specification Send feedback &A XILINX Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 3: DC Characteristics Over Recommended Operating Conditions(Cont'd) Symbol Description Min Typ( Max Units n Temperature diode ideality factor 1.010 Temperature diode series resistance 2 Notes 1. Typical values are specified at nominal voltage, 25C 2. This measurement represents the die capacitance at the pad, not including the package 3. Maximum value specified for worst case process at 25C 4. Termination resistance to a Vcco/2 level Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR l/ O Banks(1)(2) AC Voltage Overshoot %ofU@55°cto125c‖ AC Voltage Undershoot%ofU@-55°cto125c 0.40 100 0.45 617 (cco+0.55 0.50 258 0.55 11.0 cco+0.60 46.6 0.60 4.77 Vcco +0. 65 21.2 0.65 2.10 Vcco +0.70 9.75 0.70 0.94 CCo+0.75 4.55 0.75 0.43 cco+0.80 2.15 0.80 0.20 CCo+0.85 1.02 0.85 0.09 cCo+0.90 0. 49 0.90 0.04 cCo+0.95 0.24 095 0.02 Notes: 1. a total of 200 ma per bank should not be exceeded 2. The peak voltage of the overshoot or undershoot, and the duration above Vcco +0. 20V or below GND-0.20V, must not exceed the values in this table DS181(v124)Aprl4,2018 www.xilinx.com Product Specification Send feedback 4 &A XILINX Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 5: Typical Quiescent Supply Current Speed Grade Symbol Description Device 1.0V 0.95v 09v Units 2 2LE 1 -1L 2LE IcciNTQ Quiescent VCCINT Supply currentXC7A12T 48 48 48 48 43 38 XC7A15T 95 95 95 58 66 mA XC7A25T 48 48 48 48 43 mA XC7A35T 95 95 95 58 mA XC7A50T 95 58 66 m A XC7A75T 155 155 155 155 96 108 mA XC7A100T 155 155 155 155 96 108 mA XC7A200T 328 328 328 328 203 232 m A XAZA12T NA 48 N/A 48 N/A NA mA XA7A15T NA 95 N/A 95 N/A N/A mA XA7A25T N/A 48 N/A N/A N/A A XAZA35T NA 95 N/A 95 NA NA A XA7A50T NA N/A 95 N/A NA m XA7A75T NA 155 N/A 155 NA NA XA7A100T N/A 155 N/A AAA 155 N/A NA XQ7A50T N/A 95 N/A 95 NA mA XQ7A100T N/A 155 NA 155 NA mA XQ7A200T NA 328 NA 328 203 NA mA Quiescent Vcco supply current XC7A12T XC7A15T 111 m AAA XC7A25T ⅩC7A35T A XC7A50T mA XC7A75T 4 4 4 4 4 mA XC7A1O0T 4 4 4 4 4 4 XC7A200T 5 5 5 mA XAZA12T NA N/A N/A NA mA XA7A15T N/A N/A N/A N/A mA XA7A25T N/A N/A NA N/A mA XA7A35T N/A n/A N/A mA XA7A50T NA N/A N/A N/A nA XAZA75T NA 4 NA 4 NA NA mA XAZA100T N/A 4 NA NA N/A mA XQ7A50T NA NA N/A mA XQ7A100T N/A 4 NA 4 NA mA XQ7A200T N/A N/A 5 5 n/A mA DS181(v124)Aprl4,2018 www.xilinx.com Product Specification Send feedback 5 &A XILINX Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 5: Typical Quiescent Supply Current (Cont d) Speed grade Symbol Description Device 1.0y 0.95V 09V Units 2 -2LE -ILI 2LE ccauxo Quiescent VccAux supply current XC7A12T 13 13 13 13 13 13 mA XC7A15T 22 22 19 m A XC7A25T 13 13 13 13 13 13 mA XC7A35T 22 22 22 22 19 22 mA XC7A50T 22 22 22 19 22 nA XC7A75T 36 36 36 36 32 36 MA XC7A1O0T 36 36 36 mA XC7A200T 73 73 mA XAZA12T NA 13 NA 13 N/A NA mA XA7A15T NA 22 NA 22 N/A N/A mA XA7A25T NA 13 NA 13 NA NA m A XAZA35T N/A 22 N/A N/A NA mA XA7A50T N/A 22 NA N/A N/A mA XA7A75T N 36 A NA A XAZA100T N/A 36 N/A N/A N/A mA XQ7A50T N/A 22 N/A 22 19 N/AmA XQ7A100T N/A 36 NA 36 32 N/A A XQ7A200T NA 73 N/A 73 65 NA mA DS181(v124)Aprl4,2018 www.xilinx.com Product Specification Send feedback 6 &A XILINX Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 5: Typical Quiescent Supply Current (Cont d) Speed grade Symbol Description Device 1.0y 0.95V 09V Units 2 -2LE -ILI 2LE CCBRAMo Quiescent VCCBRAM Supply current XC7A12T mA XC7A15T 2 2 111 m A XC7A25T mA XC7A35T 2 2 mA XC7A50T XC7A75T 2244 12244 2 1212244 nA MA XC7A1O0T 2 mA XC7A200T mA XAZA12T N/A NA N/A N/A mA XA7A15T NA 2 NA 2 N/A N/A mA XA7A25T N/A NA NA NA m A XAZA35T N/A N/A 2 N/A NA mA XA7A50T N/A 2 NA N/A NA mA XA7A75T NA 4 A NA A XAZA100T N/A N/A 4 N/A N/A mA XQ7A50T N/A 2 N/A 2 N/A mA XQ7A100T N/A 4 NA 4 N/A A XQ7A200T NA N/A 11 NA mA notes: 1. Typical values are specified at nominal voltage, 85C junction temperature (Ti) with single-ended selectIo resources 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all l/0 pins are 3-state and floating 3.UsetheXilinxPowerEstimator(xpe)spreadsheettool(downloadathttp://www.xilinx.com/power)toestimatestaticpowerconsumptionfor conditions other than those specified DS181(v124)Aprl4,2018 www.xilinx.com Product Specification Send feedback &A XILINX Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Power-On/Off Power Supply Sequencing The recommended power-on sequence is VcciNT, VCCBRAM, VCCAUX, and Vcco to achieve minimum current draw and ensure that the iy Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VccinT and vccbram have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VccAux and vcco have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously For Vcco voltages of 3. 3V in HR I/O banks and configuration bank 0 The voltage difference between Vcco and vccaux must not exceed 2.625V for longer than Ty CCO2VCCAUX for each power-on/off cycle to maintain device reliability levels e TvCco2vccaux time can be allocated in any percentage between the power-on and power-off ramps The recommended power-on sequence to achieve minimum current draw for the gtp transceivers is VcciN, VMGTAVCC power-off sequence is the reverse of the power-on sequence to achieve minimum current dray usly the recommended VMGTAVTT OR VMGTAVCC, VCCIN, VMGTAVTT Both VMGTAvcc and vccint can be ramped simultane If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power- up and power-down. When VMGTaVTT is powered before VMGTAvcc and VMGTaVTt-VMGTAvcc >150 mV and VMGTavcc <0.7V, the VmgtaVtt current draw can increase by 460 mA per transceiver during VMGTAvcc ramp up. The duration of the current draw can be up to 0.3 X TMGTAvcc (ramp time from gnd to 90% of vmGtavcc. the reverse is true for power-down When VMGTaVTT is powered before Vccint and VMGTAVTt -Vccint>150 mV and vccint <0.7V, the VMGTAVTT current draw can increase by 50 mA per transceiver during VcciNT ramp up. The duration of the current draw can be up to 0. 3 X TVCCINT (ramp time from GNd to 90% of VccinT) The reverse is true for power-down There is no recommended sequence for supplies not shown Table 6 shows the minimum current, in addition to Icc, that is required by Art]x-7 devices for proper power-on and configuration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four supplies have passed through their power-on reset threshold voltages. The FPga must not be configured until after Vccint is applied Once initialized and configured, use the Xilinx Power Estimator(XPE) tools to estimate current drain on these supplies Table 6: Power-On Current for Artix 7 Devices Device CHIntiN CCAUXMIN COmIN CCBRAMMIN Units XC7A12T ICcINTQ+ 120 CCAUXQ 40 IcCoQ+40 mA per bank CCBRAMQ+ 60 XC7A15T Cc|Q+120 ICCAUXQ 40 ccoQ+ 40 ma per bank lCCBRAMQ+60 nn AA XC7A25T ICCINTO 120 ICCAUXO +40 ICCOo 40 mA per bank ICCBRAMO 60 mA XC7A35T CCINTQ 120 ICCAUXO 40 IcCoQ+40 mA per bank ICCBRAMO+60 mA XC7A50T CCINTQ+ 120 ICCAUXO 40 IcCoQ+40 mA per bank CCBRAMQ+ 60 mA XC7A75T CCINTQ+ 170 lce ICCAUXO +40 ccoo +40 mA per bank cCBRAMo+ 60 mA XC7A1O0T ccINTQ 170 ICCAUXQ 40 ccoQ+ 40 ma per bank CCBRAMQ +60 mA XC7A200T CCINTQ+ 340 ICCAUXQ +50 IccoQ +40 mA per bank CCBRAMQ +80 mA XAZA12T ICCINTQ +120 ICCAUXQ 40 IcCoQ+40 mA per bank ICCBRAMO +60 mA XA7A15T ccINtQ 120 CCAUXQ+ 40 IcCoQ +40 mA per bank CCBRAMQ+ 60 mA XA7A25T CCINTQ+ 120 CCAUXO 40 IccoQ +40 mA per bank CCBRAMQ +60 mA XAZA35T CCINTQ+ 120 CCAUXQ +40 lccoa+40 ma per bank IccBRAMQ+60 mA XAZA5OT ICCINTQ 120 ICCAUXQ +40 IccoQ+40 mA per bank CCBRAMQ +60 mA XAZA75T CCINTQ +170 CCAUXQ +40 ICcoQ+ 40 mA per bank CCBRAMQ +60 mA XAZA100T ccINtQ+ 170 CCAuXQ F 40 ICCoQ +40 mA per bank CCBRAMQ+ 60 mA ⅩQ7A50T IccINTQ 120 CCAUXQ 40 Iccoo +40 mA per bank CCBRAMQ 60 mA DS181(v124)Aprl4,2018 www.xilinx.com Product Specification Send feedback &A XILINX Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 6: Power-On Current for Artix-7 Devices(Contd) Device ICCINTMIN CCAUXMIN CCOMIN CCBRAMMIN Units ⅩQ7A100T CCINTQ+170 CCAUXQ+40 CCoQ+40 mA per bank CCBRAMQ+60 mA XQ7A200T CCINTQ +340 ICCAUXQ 50 IccoQ+ 40 mA per bank CCBRAMQ+ 80 mA Table 7: Power Supply Ramp Time Symbol Description Conditions Min Max Units VCCINT Ramp time from GNd to 90% of Vccint 0.2 50 ms T Ramp time from GNd to 90% of Vcco 0250 ms TyCCAUX Ramp time from GNd to 90% of VccAUX 02 ms VCCBRAM Ramp time from GNd to 90% of VccBRAM 0.2 50 ms TJ=125°c(1) 300 VCco2VCCAUX Allowed time per power cycle for V. CCo-V CCAUX >2.625V TJ=100°C(1) 500 ms TJ=85°c() 800 MGTAVCC Ramp time from GNd to g0% of VMGTAvCC 0.2 50 ms MGTAVTT Ramp time from GNd to 90% of VmgtaVtt 0.2 50 ms Notes. 1. Based on 240,000 power cycles with nominal Vcco of 3. 3v or 36, 500 power cycles with worst case Vcco of 3. 465V DC Input and Output Levels alues for Vil and vih are recommended input voltages. values for iol and loh are guaranteed over the recommended operating conditions at the Vo and voh test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum Vcco with the respective Vor and Voh voltage levels shown Other standards are sample tested Table 8: SelectIO DC Input and output Levels( 1)(2) v VoL v OH yO Standard V Min V Max V Min V Max V. Max V Min mA, Max mA. Min HSTL I 0300VREF-0.100VREF+0.100Vcc0+0.300 0.400 vco=0400800 8.00 HSTL 18 0300VREF-0.100VREF+0.100Vcc0+0.300 0400 cco-04008.00-800 HsTL‖ -0300=F-0.100V=F+0100Vc0403000400Vc0-04001600-16 HsTL‖18 030vF-010yeF+01060400040604016001600 HSUL 12 030VF-010VF+0130V6co0+03020%o80%yco010010 LVCMOS12 030035%∨cco 65% Vcco vcco+03000400 Vcco-0400 Note 3 Note 3 LVCMOS15 030035%Vcco 65% VccoVcco+0.300 25%Vcco 75%Vcco Note 4 Note 4 LVCMOS18 0.30035%V Cco 65%Vcco Vcco +0.300 0.450 Vcco-0450 Note 5 Note 5 LVCMOS25 0.300 0.7 1.700 Vcco +0.300 0.400 Vcco.400 Note 4 Note 4 LVCMOS33 0.300 08 2.000 3.450 0.400 Vcco-0400 Note 4 Note 4 LVTTL 0.300 08 2.000 3.450 0.400 2.400 Note 5 Note 5 MOBILE DDR 0.300 20%V CO 80% Vcco vcco04030010%Vo90%vo0 0.10 0.10 Pc|333 040030%V 50% Vcco Vco+0.50010%co 90%V CCo 1.50 -0.50 SSTL135 0300VREF-0.090VREF+0090Vco+0300Vco2-0.150V2+0.1501300-1300 SSTL135 R 0300VEF-0.090V REF+0.090V cco+0300Vc2-0.150Vc2+0.1508.90 8.90 SSTL15 0300VEF-0.100VAEF+0.100Vcco+0.300Vcc2-0.175Vco2+0.1751300-1300 DS181(v124)Aprl4,2018 www.xilinx.com Product Specification Send feedback &A XILINX Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 8: SelectIO DC Input and output Levels(1)(2)(Cont'd OL OH OH 1O Standard V Min V Max V Min V Max V Max V, Min mA, MaxmA, Min SSTL15 R -030VREF-01VREF010000c092015vo2+017589090 SSTL18 0300VEF-0125VHEF+0125Vco0+000c02-0470V2+0.4708006 800 SSTL18‖ 0300VREF-0.125VREF+0.125Vcc0+0.300Vco2-0600vcco2+06001340-1340 Notes 1. Tested according to relevant specifications 2. 3.3V and 2. 5v standards are only supported in HR l/O banks 3. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks 4. Supported drive strengths of 4, 8, 12, or 16 mA in HR l /O banks 5. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR O banks 6. For detailed interface specific Dc voltage levels, see 7 Series FPGAs Select/O Resources User Guide(UG471) Table 9: Differential SelectIO DC Input and Output Levels ICM v OCM (3) Von(4) 1o Standard V,MinV, Typ V, Max V, Min/, Typ V, Max V, Min V, Typ V, Max V, MinV,TypV,Max BLVDS250300120014250.100 1.250 Note 5 MIN LVDS2503001200 VCcAUX0200040006001.000 1.200 14000.30004500600 PPDS 25 02000.900V CCAUX 0100025004000.500 0.950 1.400 0.10002500400 RSDS 25 030009001500010003500.6001.000 1.200 1400010003500.600 TMDS332.70029653230015006751200Vc00405vcc-0.300V00.19004000.6000.800 Notes: 2.CM is the input common mode voltage D is the input differential voltage( Q-Q) OCM is the output common mode voltage. oD is the output differential voltage(Q-Q) 5. VoD for BLVDS will vary significantly depending on topology and loading Table 10: Complementary Differential SelectIO DC Input and output Levels VICM v v OL VOH (4) OH 10 Standard V, Min V, Typ V, Max V, Min V,Max V, Max V. Min mA. Max mA. Min DIFF HSTL I 030007501.1250.100 0.400 Vcco-0 400 8.00 800 D| FF HSTL I180.3000.9001.4250.100 0.400 VcCo-0400 8.00 8.00 DIFF HSTL‖ 0.3000.7501.1250.100 0.400 Vcco. 400 16.00 1600 D| FF HSTL‖1180.3000.9001.4250.100 0.400 Vcco 0.400 16.00 1600 DIFF HSUL 12 030006000.8500100 20%Vcco 80%Vcco 0.100 0.100 D|FF_ MOBILE DDR0.30009001.4250.100 10%Vcco 90% Vcco 0.100 -0.100 DIFF SSTL135 030006751.0000.100 Vcco2)-0.150Vc/2)+0.150 13.0 -13.0 D| FF SSTL135R0.30006751.0000.100 Vcco2)-0.150co/2)+0.150 8.9 8.9 DIFF SSTL15 0.30007501.1250.100 Vcco2)-0.175(Vcc02)+0.175 13.0 130 D| FE SSTL15R0.30007501.1250100 vcco2)-0.175co/2)+0.175 8.9 8.9 DIFF SSTL18 0300090014250100 vcc2)-0470vcc02)+0470 8.00 -8.00 DS181(v124)Aprl4,2018 www.xilinx.com Product Specification Send feedback 10

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