VERILOG 74hc3738D 锁存器模型
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2010-09-06
14:39:58
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74HC373.zip （60个子文件） 
74hc373 simulation 
vsim.wlf 40KB modelsim.ini.sav 281B modelsim.log 1KB presynth testbench _primary.dbs 977B _primary.vhd 78B _primary.dat 796B verilog.psm 6KB _vmake 26B _temp latch8 _primary.dbs 605B _primary.vhd 298B _primary.dat 350B verilog.psm 4KB _info 572B modelsim.ini 281B run.do 566B designer impl1 latch8.dtf verify.log 233B simulation latch8.adb 48KB latch8.ide_des 600B latch8.tcl 172B latch8.pdb.depends 0B latch8.pdb 17KB latch8_fp latch8.log 1KB projectData latch8.pdb 17KB latch8.pro 2KB $$FlashPro_07294.L$$ 143B designer.log 443B hdl 74hc373.v 1KB viewdraw sch sym vf project.lst 47B viewdraw.ini 2KB wir coreconsole smartgen smartgen.aws 366B constraint component phy_synthesis synthesis stdout.log 870B latch8_sdc.sdc 375B latch8.map 28B
run_options.txt 1KB latch8_syn.sdc 1KB latch8.srr 10KB latch8.fse 0B latch8.htm 328B backup latch8.srr 10KB latch8_syn.prj 1KB latch8_syn.prd 272B latch8.srd 3KB coreip latch8.szr 10KB latch8.areasrr 669B latch8.edn 14KB latch8.sap 885B latch8.so 205B latch8.pdc 129B latch8.srm 137KB syntmp latch8_srr.htm 14KB latch8_flink.htm 339B latch8_toc.htm 752B latch8.plg 97B sap.log 642B latch8.tlg 4KB latch8.sdf 350B latch8.srs 3KB 74hc373.prj 4KB stimulus testbench.v 762B
74hc373.pdf 220KB资源评论
yangzhanfeng37222014-01-03不错，是周立功的actel的开发例程
u0107844082014-01-03挺不错的 比较有用~
