pg066-jesd204

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一种新型的基于高速SERDES的ADC/DAC数据传输接口。ADC/DAC的采样速率变得越来越高,数据的吞吐量越来越大,对于500MSPS以上的ADC/DAC,动辄就是几十个G的数据吞吐率,采用传统的CMOS和LVDS已经很难满足设计要求,JESD204B应运而生。现在各大厂商的高速ADC/DAC上基本都采用了这种接口
sXL|NⅩ ALL PROGRAMMABLEN Simulation ...... 95 Synthesis and Implementation 95 Chapter 5: Example Design Common Design Elements. 97 Chapter 6: Test bench Appendix A: Verification, Compliance, and Interoperability Simulation 109 ardware testing 109 Appendix B: Hardware Demonstration Design Appendix C: Migrating and Upgrading Migrating to the vivado Design Suite 111 Upgrading in the Vivado Design Suite 111 Appendix D: Debugging Finding help onⅪ Hlinx, con,∴,…,,,,,,121 Debug tools...,.. ..122 Simulation Debug. ,,,。,,,,,124 Hardware debug... 125 Interface debug 126 Appendix E: Additional Resources and Legal Notices Xilinx Resources 127 References 127 Revision History...... 128 Please Read: Important Legal Notices 131 JESD204 V72 www.xilinx.com Send feedback PG066 October 4, 2017 XL|NⅩ IP Facts ALL PROGRAMMABLE Introduction LogiCORE IP Facts Table ore Specifics The Xilinx logicoRETM IP JESD204 core UltraScale+m ultrascaletm implements a JESD204B interface supporting Supported Zynq @-7000 All Programmable Soc, line rates from 1 Gb/s to 12.5 Gb/s(1).the Device Family(1) Artix- virtex -7 Kintex-7 JESD204 core can be configured as a Supported User transmitter or receiver. (2) Interfaces AX14-Stream, AX14-Lite Control/Status Resources Performance and Resource Utilization web page Provided with core Features Design Files Encrypted rtL Example design erilog Designed to JEDEC R JESD204B [Ref 1 Test bench Verilog Supports up to 8 lanes per core and up to Constraints file XDO 32 lanes using multiple cores Simulation Model Verilog Supports Initial Lane alignment Supported N/A Supports scrambling S/W Drive Supports 1-256 octets per frame (3) Tested Design Flows(2) Design Entry Vivado⑧ Design Suite Supports 1-32 frames per multiframe (3) Simulation For supported simulators, see the Supports Subclass 0,1, and 2 Xilinx Design Tools: Release Notes guide these Vivado Synthesis hysical and data Link Layer functions Support provided Provided by Xilinx at the Xilinx Support web page AXl4-Lite configuration interface [Ref 2] Notes: AX 4-Stream data interface [ref 3 For a complete listing of supported devices, see the Vivado IP catalog Supports transceiver sharing between TX 2. For the supported versions of the tools, see the and rx cores using the jesd204 PHY core Xilinx Design Tools: Release Notes Guide 1. Non-standard line rates up to 16.375 Gb/s are supported 2. The maximum line rate supported is dependent on the transceiver type and speed grade of the selected device For UltraScale devices with GTHE4/GTYE4 transceivers the line rate is also limited by the maximum frequency specified for TXUSRCLK/RXUSERCLK (core clock) with 40-bit Interconnect Logic Data width. For these devices the maximum line rate is tX/RXusrclk *40 Please see the relevant device data sheet 3. The maximum supported multiframe size is 1000 octets and the minimum is 20 octets JESD204 V72 www.xilinx.com end seedlac PG066 October 4, 2017 Product specification ⅩL|NX ALL PROGRAMMABLEIN Chapter 1 Overview The LogicoRETM IP JESD204 core implements a JESD204B interface supporting line rates between 1 and 12.5 Gb/s()on 1 to 8 lanes using GTX, GTH, GTP or GTY(UltraScale and UltraScale+ only)transceivers. See the device data sheets for maximum line rates supported by each device and family the jesd204 core can be configured as transmit or receive and multiple cores can be used to realize links requiring greater than 8 lanes The JESD204 core is a fully-verified solution design delivered by using the Xilinx vivado Design Suite. In addition, an example design is provided in Verilog Transmitter Figure 1-1 shows an overview block diagram for the transmitter of the JESD204 core JESD204 Transmitter Core Genera AX14-Streamh+Scrambler ESD204 ane Serial data Alignment RPAT Generato SynC/SYSREF IX Counters JSPAT enerator Ax 4-Lite G AX 4-Lite/PIF Control Figure 1-1: Transmitter Core Overview Non-standard line rates up to 16. 375 Gb/s are supported JESD204 V72 www.xilinx.com Send feedback PG066 October 4, 2017 K XILINX Chapter 1: Overview The main blocks are Single axl4-Stream interface for all lanes TX lane logic, per lane contains 。 Scrambling Alignment character insertion logic Initial Lane Alignment(ILA) sequence generation TX Counters-control, state machine and syNc/sysref interface JESD204_PHY containing the transceivers RPAT generator JSPAT generator AXl4-Lite Management interface and control /status registers Receiver Figure 1-2 shows an overview block diagram for the receiver of the JESD204 core JESD204 Receive Core RX Lane(s) Descrambler H Alignment Replac JESD204 erial data 8 HAXI4-Stream Decode Lane Alignment Sequence SYSREF MFC and Sync Statu AX14-Lite AX 4-Lite/IPIF Control Figure 1-2: Receiver Core overview The main blocks are Single aXl4-Stream interface for all lanes RX lane logic, per lane, contains ILA capture 。 Descrambling Alignment character detection and replacement logic JESD204 V72 www.xilinx.com Send feedback PG066 October 4, 2017 K XILINX Chapter 1: Overview Local multiframe clock (lmfc)state machine and syNc/sysreF interface JESD204_PHY containing the transceivers Error counters for each lane AXI4-Lite Management interface and control/status registers Core Level architecture The JESD204 core is delivered by the vivado design Suite with supporting wrapper files Either a jesd204b transmitter core or a jesd204b receiver core can be selected for generation using the Vivado IDE Core-level Verilog wrappers are provided to instantiate the JESD204 lP, the clock/reset logic, Management block, the JESD204_PHY transceiver, the JSPAT and RPAt pattern generator blocks, and the Error Counting blocks depending on whether the core is a transmitter or a receiver. The core support layer, delivered with the example design, is intended for instantiation in simple unidirectional designs The Management block provides core Control and Status registers with a standard AX14-Lite interface. The rPat and SPAt blocks are optional test pattern generators which can be included in a TX core Link Error counter blocks are included in a receiver core to support data link layer test modes and link status monitoring A Verilog example design is provided which instantiates the core-level wrapper, together with example interface modules. this is a device-level design and can be used to run the core through the Xilinx tool flow but is not intended to be used directly in customer designs The transmit and receive logic is completely independent; a core can be generated as a transmitter or a receiver. The core can be generated with the JESD204 PHY, instantiated either: Inside the core for basic simplex applications Inside the example design for applications that require sharing the transceivers with other JESD204 cores(e.g, TX and RX sharing transceivers)or access to the extended features available using JESD204 PHY AXI-lite register interface(see Shared Logic Tab) JESD204 V72 www.xilinx.com Send feedback PG066 October 4, 2017 K XILINX Chapter 1: Overview Applications JESD204 is a high-speed serial interface designed to connect Analog-to-Digital Converter (ADCS)and Digital-to-Analog Converter(DACs) to logic devices. The JESD204 interface is specified in the /EDEC B JESD204B Specification [Ref 1]. Figure 1-3 and Figure 1-4 show how the JESD204 provides the interface between an ADC/DAC and user logic over an example four lane interface ADC Device FPGA 4 Lanes ADC ADC 12138 Figure 1-3: Example ADC application FPGA DAC Device 4 Lanes User Logic -寸oNo∽ Ym寸ONo∽u DAC DAC x12139 Figure 1-4: Example DAC Application Unsupported Features Sample data mapping/demapping is not provided by the core, because of the requirement that it be customized for different converter devices. For more information, see Interfacing to the ax 4-Stream Data Interface JESD204 V72 www.xilinx.com Send feedback PG066 October 4, 2017 K XILINX Chapter 1: Overview Licensing and Ordering Information License checkers If the IP requires a license key, the key must be verified. The vivado design tools have several license checkpoints for gating licensed iP through the flow. If the license check succeeds, the ip can continue generation otherwise generation halts with error. license checkpoints are enforced by the following tools Vivado synthesis Vivado implementation write bitstream(tcl command) IMPORTANT: P license level is ignored at checkpoints. The test confirms a valid license exists. /t does not check ip license level License Type This Xilinx LogicoRE IP module is provided under the terms of the Xilinx Core License Agreement. The module is shipped as part of the vivado design Suite. For full access to all core functionalities in simulation and in hardware, you must purchase a license for the core Contact your local Xilinx sales representative for information about pricing and availability For more information, visit the JESD204 product web page Information about other Xilinx LogiCoRE IP modules is available at the Xilinx Intellectual Property page For information on pricing and availability of other Xilinx logICORE IP modules and tools, contact your local Xilinx sales representative A free evaluation version of the core is provided with the Xilinx Vivado design Suite which lets you assess the core functionality and demonstrates the various interfaces of the core in simulation. To access the evaluation version visit the JESD204 IP Evaluation page JESD204 V72 www.xilinx.com Send feedback 9 PG066 October 4, 2017 K XILINX Chapter 1: Overview License options The JESD204 core provides three licensing options. After installing the vivado design Suite and the required IP Service Packs, choose a license option Simulation Only The Simulation Only Evaluation license key is provided with the Xilinx Vivado Design Suite This key lets you assess core functionality with either the example design provided with the JESD204 core, or alongside your own design and demonstrates the various interfaces to the core in simulation. (Functional simulation is supported by a dynamically generated HDL structural model.) Full System Hardware Evaluation The full System Hardware Evaluation license is available at no cost and lets you fully integrate the core into an FPga design, place-and-route the design, evaluate timing, and perform functional simulation of the JESD204 core using the example design and demonstration test bench provided with the core In addition the license key lets you generate a bitstream from the placed and routed design, which can then be downloaded to a supported device and tested in hardware. The core can be tested in the target device for a limited time before timing out(ceasing to function), at which time it can be reactivated by reconfiguring the device The full license key is available when you purchase the core and provides full access to all core functionality both in simulation and in hardware, including Gate-level functional simulation support Back annotated gate-level simulation support Functional simulation support Full-implementation support including place and route and bitstream generation Full functionality in the programmed device with no time-outs JESD204 V72 www.xilinx.com Send feedback 10 PG066 October 4, 2017

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