英飞凌AURIX TC26x B-Step芯片用户手册，详细讲解了TC26x的各个模块的设计和使用，全文5705页，是开发工程师的必备手册
ntineon AURIXTM TC26X B-Step 32-Bit Single-Chip Microcontroller User's manual V1.32014-12 Microcontrollers Infineon TC26x B-Step TC26x B-Step User's Manual Revision History: V1.3 2014-12 Significant changes since previous version: TC26x User's Manual V1.2 Chapter Subjects(major changes since last revision) ntroductio Removed redundant introduction sections FIRMWAR. Added description of the CRC calculation method below the table"Boot E Mode Header (BMHD) SCU/CCU. Updated divider formula in registers CCUCON6,7,8 Updated table CcU allowed clock Ratios SCU/SCU Corrected dtscon cal width Removed design related register reference from "ocds behavior of WDTs” PORTS. Corrected description of LVDs pads in CMOS mode: removed sentence no open-drain mode available MTU MCONTROL. Res4 field(bits 14: 12)marked as "Must be written with 0X4 in to maintain redundancy Sections "Reading a Single Memory Location"and"Writing a Single Memory location"should always write control with the ms nibble 0x4 instead of oxo Design related register reference"RDR"removed User's manual V1.3,2014-12 Infineon TC26x B-Step TC26X B-Step User's Manual Revision History: V1.3 2014-12 SMU Corrected register long name of SMU Rtc to Recovery Timer Configuration DMA alarm ALM2[24] is now reserved. Alarm implemented by DMA sri error detection alarms Improved description of alarm ALM3[271 SCU alarm ALM3 [28] is now reserved Feature not implemented Pre-alarms PreAlarm[ 129=DMA. Safety FF Error Detection)an PreAlarm[ 130=PMU (Safety FF Error Detection)] removed because DMA and pmu do not implement Safety FF Added configuration hints to SMU AG<n>CF<m> Registers: reserved alarms shall be configured as " No Action Enhanced description of register SMU RMEF and SMU RMSTs Enhanced description of register SMU PCTL with advice how to operate it in the application Changed section "SMU Integration Guidelines Explained“ Register Monitor”=“ Safety Flip-Flop”. Improved Figure "SMU State Machine Improved section"FSP Fault State User's manual 1-2 V1.3,2014-12 Infineon TC26x B-Step TC26X B-Step User's Manual Revision History: V1.3 2014-12 PMU Highlighted in the description of Fcon and the wait cycle description that after System Resets and Power-On Resets the wait cycles are only sufficient for 100 MHz Noted in the "Application Hints" that the recommended sequence for issuing "Verify Erased Logical Sector Range"is analog to"Erase Changed recommendations in the Application Hints"for ECc test patterns. Made the all-O/all-1 and address error patterns optional Recommended to store 2 of the 4 pattern sets inverse to the other 2 Improved description of "Load Page to make the offsets used for 32-bit transfers more explicit Added to the description of "Write Page"the clear statement that each page shall be programmed only once Noted that "Verify Erased Logical Sector Range" is not blocked on password containing UCBs when the protection is disabled Removed confusing statement that unavailable dFlash ranges can be programmed to all-1 Noted explicitly that the UCBs 8 to 11 are read-only Clarified that both Write Page"and Write Burstcan be used to program UCBs Removed statement about restricted FAR capabilities Removed note from Erase logical Sector Range" that warned from erasing more than 256 KByte because of increased suspend times. The suspend times are not increasing Changed note for Erase Logical Sector Range" that described that erase time can be much shorter than maximum times documented in the data sheet the reason was removed as there are more dependencies · Documented“ Test Pass marker"in UCB|FⅩ Removed term "Reset Class" and replaced by named resets Stated explicitly that a failed HSm boot prevents device boot R Added clarification: a pending Service Request is cleared in the Service Request Node with the Acknowledge from the Service Provider. The Acknowledge does not mean that the Service Request is serviced at that time(e.g. disabled or not implemented DMA channel, Trap on CPU prevents execution of Service Request ASCLIN B|ock“ Auto Baud rate operation” added Description of register field "BRD. MEASURED" improved User's manual 1-3 V1.3,2014-12 Infineon TC26x B-Step TC26X B-Step User's Manual Revision History: V1.3 2014-12 QSP Removed maximum baud rates from feature list as these depend on pad speeds and PCB implementation MSC Description of Clock Control when using the ABRA block "improved Equation of cycles for extended frames changed added factor 32 to PPDE MultIcan+·Fiⅸ ed pad naming for all devices cRc issue of can fd standard documented and recommended additional software crc SENT Updated serial Message frame chapter GTM Corrected error in bGa-416 ToUT numbering for p10.13 and P10. 11 Connection shown in figures and register for set5 and set6 to Msc2 was corrected Updated description of bit field OCs. SUs Updated description of (A)TOM SOMP Mode Clarified reset behavior of debug registers Corrected error for p2.11 it is connected to tim4 4 not to tim4 7 VADC Added hint how to use Pxx PDisc for diagnostics in section "Signal Path Test modes Adjusted the position of accumulated results in section Data Alignment DSADc. Changed in section"Recommended Settings"the documented full scale values from +1900 to +3800n and their dependence on operating modes Removed external modulator connections Removed modulator combine mode Separated rectifier and integrator, add data shift in figure DSADC structure overview User's manual 14 V1.3,2014-12 Infineon TC26x B-Step Trademarks TriCore is a trademark of Infineon Technologies ag Copyrights Portions Copyright o 2013 Synopsys, Inc. Used with permission. All rights reserved Synopsys design Ware are registered trademarks of Synopsys, Inc We listen to your comments Is there any information in this document that you feel is wrong, unclear or missing? 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INc. zeteXtm of diodes zetex limited Last Trademarks Update 2011-11-11 User's manual V1.3,2014-12 Infineon TC26x B-Step Table of contents Table of contents TC26x B-Step Introduction About this document 1.1.1 Related documentations 1-1 1.1.2 Text Conventions 1.1.3 Reserved, Undefined, and Unimplemented Terminology 1.1.4 Register Access Modes 1.1.5 Abbreviations and acronyms ..1-4 System Architecture of the TC26X B-Step 1-8 1.2.1 TC26x B-Step block Diagram 19 On-Chip Debug Support(OCDS ..1-10 1.3.1 Feature list 1.3.2 Family Overview 1-12 1.3.3 Tool Interface Recommendations 1-13 1.3.4 Debug Access Server(DAS) 1-15 1.4 Emulation Device(ED 1-16 1.4.1 Block Diagram 1-16 1.4.2 Feature list 1-18 1.4.3 Comparison to TC27XED 1-19 1.4.4 Trace Based measurement 1-20 1.4.5 ED Design and layout 1-21 1.4.6 Emulation System Components 1-21 1.4.6.1 Emulation Memory(EMEM) 1-21 1.4.6.2 Calibration Memory 1-22 1.4.6.3 Trace Memory 1-22 1.4.7 MCDS 1-23 1.4.8 DAP/JTAG based Tool Interface(IOC32) 124 1.4.9 Aurora GigaBit Trace(AGBT) 1-24 2 On-Chip System Buses and Bus Bridges 2-1 2.1 What is new 2-2 2.2 SRI Crossbar(XBar SRI) 2.2.1 troduction 2-3 2.2.1.1 XBar SRI Features 2-5 2.2.2 SRI Transactions 2-5 2.2.3 SRI Op-Codes 2-6 2.2.4 SRI Error Conditions 2.2.5 SRI Transaction d Error conditions 2-7 2.2.6 Operational Overview 2-8 2.2.6.1 Functional blocks 2-9 2.2.7 Functional overview 2-12 2.2.7.1 Arbitration block 2-12 User's manual V1.3,2014-12