I2C_Timing_Configuration_V1.0.0 说明书

所需积分/C币:50 2019-05-07 08:53:49 392KB PDF
收藏 收藏

I2C_Timing_Configuration_V1.0.0 配套说明书,用来配置stm32F0 F3系列I2C timing,按照说明书配置,很简单
AN4235 List of tables List of tables Table 1. Applicable products Table 2. Definition of terms Table 3. 12C timings specification(see 12C specification rev 03, June 2007) 8 Table 4. Document revision history 17 Doc D 024161 Rev 1 3/18 List of figures AN4235 List of figures Figure 1. 12C bus timing(see 12C specification, rev. 03, June 2007) Figure 2. 12C clock scheme Figure 3. Timing register ,,.,10 Figure 4. Data setup time generation from SCLDEL 10 Figure 5. Data hold time generation from SDADEL 11 Figure 6. High and low period generation from SCLH and SCLL Figure 7 12C timing configuration tool user interface .·::·:·:· 13 Figure 8. Calculation is completed 14 Figure 9. Error message 15 4/18 Doc D 024161 Rev 1 AN4235 Glossary Glossary Table 2 Definition of terms Term Description AF Analog filter DN Digital noise filter HSI High-speed internal clock 12C Inter circuit communication 12CCLK 12C kernel clock PCLK APBx clock PRESC Prescaler SCL Serial clock line SDA Serial data line SYSCLK System clock Doc D 024161 Rev 1 5/18 Getting started AN4235 Getting started This section describes the requirements and procedures needed to start using the timing configuration tool 2.1 Software requirements To use the timing configuration tool with Windows operating system, a recent version of Windows, such as Windows xP Vista or Windows 7, must be installed on the pc with at least 256 Mbytes of RAM Before starting to use the timing configuration tool, make sure that microsoft office is installed on your machine and then follow these steps Download the latest version of the 12c timing configuration tool for the stm32 devices from www st com Enable macros and activex controls as shown below Excel 1997-2003 version 1. Click Tools in the menu bar 2. Click Macro 3. Click Security 4. Click Low(not recommended) Note If ActiveX controls are not enabled, a warning message is displayed asking you to enable ActiveX. In this case, you should click OK to enable it Excel 2007-2010 version 1. Click the Microsoft Office button and then click Excel options 2. Click Trust Center, click Trust center settings, and then click Macro settings 3. Click Enable all macros (not recommended, potentially dangerous code can run) 4. Click Trust Center, click Trust center settings, and then click ActiveX settings 5. Click Enable all controls without restrictions and without prompting(not recommended; potentiality dangerous controls can run) 6. Click。K Note For more information about how to enable macros and active x controls, refer to the Microsoft office website 6/18 Doc D 024161 Rev 1 AN4235 Getting started 22 Hardware requirements 2.2.1 Introduction The 12C timing configuration tool is designed to help the end-user easily configure the timing settings for the 12C peripheral and guarantee its operation as specified in the 12C timing specification 2.2.2 12C timing specification The 12c timings should be configured with values that are compliant with the 12c bus specification Figure 1. 12c bus timing(see 12C specification, rev. 03, June 2007 tr ISU: DAT 70% 70% SDA I 30 i 30% tHD; DAT tVD DAT 70% 70% 70 70% 30% 30% 30% cont HD. STA gth clock 1st clock cycle BUF一 tsU: STA VD: ACK tsu:STO 70% ··sCL gth clock Doc D 024161 Rev 1 7/18 Getting started AN4235 The table below shows the value range of these timings Table 3. 12C timings specification (see 12C specification, rev. 03, June 2007) Standard Fast mode Fast mode Symbol Parameter Unit Min Max Mir Max Min Max fscL SCL clock frequency 0 100 400 0 1000 KHZ tL Ow Low period of the SCL clock 4.7 0.5 HIGH High Period of the SCL clock 4 0.6 0.26 Rise time of both sda and scl 20+ tr 1000 0.1cb) 300 120 ns signals Fall time of both sda and SCL 20+ signals 01ch1)300 120 tHD: DAT Data hold time 0 0 0 LVD DAT Data valid time 3452) 09 (2) 0.452) tVD:ACk Data valid acknowledge time 3452) 0.9(2) 045(2) SU; DAT Data setup time 250 100 50 Hold time(repeated) START LHD: STAcondition 4.0 0.6 0.26 U: Sta Set-up time for a repeated START 4.7 0.2 condition 0.6 tSU: STo Set-up time for STOP condition4.0 0.6 0.26 Bus free time between a STOP and START condition 4.7 13 0.5 1. Cb= total capacitance of one bus line in pF 2. The maximum tHD DAI could be 3. 45 us, 0. 9 us and 0. 45 us for standard mode fast mode and fast mode plus, but must be less than the maximum of tVd DAT or tyD: ack by a transition time 8/18 Doc D 024161 Rev 1 AN4235 Getting started 2.23 2c clock scheme The 12C kernel is clocked by an independent clock source. the clock source can be HSI (default source) SYSCLK Figure 2. 12C clock scheme 12C Interface SYSCLK 12CCLK Timing generation RCC 2CXSW PCLK Registers MS31629V1 These two clocks allow 12C to operate independently from the PClk frequency Setting HsI as 12c clock source frequency allows the use of wake-up from STOP mode capability at address match The 12CCLK period tccLk must respect the following conditions tI2cclk <(tLow -filters)/4 and tr2cclk tHIGH filters: when enabled, sum of the delays brought by the analog filter and the digital filter Analog filter delay is maximum 260 ns and digital filter delay is dNF X t(2CCLK The pclK clock period tpclk must respect the following condition tpclk <4/3 tscl Please refer to the rcc section in STM32 product reference manual for more details about the selection of the i2C clock source Doc D 024161 Rev 1 9/18 Getting started AN4235 2.2.4 12c timing register The 12C timing register is detined as the following figure shows Figure 3. Timing register 313029282726252423 21 19 17 PRESC[3: 0 Res. Fes. Res. Res SCLDEL 3: 0 SDADEL[3: 0 1514 13 121110 8 6 2 SCLH7: 0 SCLL7: 0 PRESC[3: 0] is used to prescale 12c clock source(12CCLK) it allows the generation of a divided clock. The period of this divided clock tpREscis defined by (PRESC+1) t20 The time unit tPREsC is used for the generation of other 12C timings SCLDEL[3: 0] is used to program the data setup time(tsu: DAT)as shown in the following Figure 4. Data setup time generation from SCLDEL SCLDEL SDA lta setup SCLDEL is defined as follow 6/[tPRESCI-1<=SCLDEL SDADEL[3: 0] is used to program the data hold time(tHd: dat) as shown in the following figure 10/18 Doc D 024161 Rev 1

试读 18P I2C_Timing_Configuration_V1.0.0  说明书
立即下载 低至0.43元/次 身份认证VIP会员低至7折
  • 分享小兵

关注 私信 TA的资源
    I2C_Timing_Configuration_V1.0.0 说明书 50积分/C币 立即下载
    I2C_Timing_Configuration_V1.0.0  说明书第1页
    I2C_Timing_Configuration_V1.0.0  说明书第2页
    I2C_Timing_Configuration_V1.0.0  说明书第3页
    I2C_Timing_Configuration_V1.0.0  说明书第4页

    试读结束, 可继续读2页

    50积分/C币 立即下载 >