Document Number: CDI/IBP#: 543611
Skylake S Platform and Greenlow-
WS Platform
Design Guide
Based on Skylake S Processor
October 2014
Revision 1.0
Intel Confidential
2 Intel Confidential CDI/IBP#: 543611
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CDI/IBP#: 543611 Intel Confidential 3
Contents
1Introduction............................................................................................................ 37
1.1 Major Platform Requirements .............................................................................. 38
1.2 Terminology ..................................................................................................... 38
1.3 Reference Documents ........................................................................................ 39
1.4 Reference Documents related to Customer Reference Boards (TBD) ......................... 39
2 Stack-Up and PCB Considerations ............................................................................ 41
2.1 Introduction ..................................................................................................... 41
2.2 Printed Circuit Board (PCB) Considerations ........................................................... 41
2.3 SO-DIMM Considerations.................................................................................... 44
2.4 Core Thickness and Material Considerations .......................................................... 45
2.5 Planes on Outer Layers ...................................................................................... 46
2.6 Low Halogen Flame Retardant Stack-Up Considerations .......................................... 46
2.6.1 Low Halogen Background ........................................................................ 46
2.6.2 Choosing a Low Halogen Material ............................................................. 46
2.6.3 Electrical Limits of Low Halogen Material Properties..................................... 47
2.7 Reference Planes............................................................................................... 47
2.8 Type 3 PCB Via ................................................................................................. 48
2.9 Thin Mini-ITX Design Considerations .................................................................... 50
2.10 6-Layer Dual-Stripline Support............................................................................ 51
2.11 Backward and Forward Coupling Coefficient Calculation .......................................... 52
2.12 Single-Ended and Differential-Routing Geometries ................................................. 54
2.13 Generalized 4-Layer Motherboard Example ........................................................... 55
2.14 Generalized 6-Layer Motherboard Example for SKL AIO .......................................... 56
2.15 Minimizing the Effect of Fiber Weave .................................................................... 56
2.15.1 Overview of Fiber Weave......................................................................... 56
2.15.2 Fiber Weave Effect versus Transfer Rate and Trace Length........................... 59
2.15.3 Specific Routing Configurations ................................................................ 59
2.15.4 Offset Routing ....................................................................................... 59
2.15.5 Zig-Zag or Slanted Routing...................................................................... 60
2.15.6 Image Rotation ...................................................................................... 61
2.15.7 Using Alternate PCB Materials .................................................................. 62
2.16 Skylake Client Signal Integrity Tool Suite ............................................................. 62
3 General Differential Design Guidelines..................................................................... 65
3.1 General Differential Stackup Guidelines ................................................................ 65
3.1.1 Stackup and Layer Utilization Guidelines.................................................... 65
3.1.1.1 General Dual-Stripline Support ................................................... 65
3.2 General Differential Routing Guidelines................................................................. 67
3.2.1 Breakout Example and Guidelines............................................................. 67
3.2.2 Differential I/O Routing Scheme Guidelines................................................ 68
3.2.3 Via Placement and Via Usage Optimization................................................. 72
3.2.4 Bend Optimization Guidelines................................................................... 74
3.2.5 General Routing Guidelines...................................................................... 75
3.3 General Differential Length Matching Guidelines .................................................... 75
3.3.1 Length Matching and Length Formulas ...................................................... 75
3.4 General Differential Compensation and Voltage Reference Guidelines ....................... 78
3.4.1 RCOMP Signal Guidelines......................................................................... 78
3.4.2 Reference Planes.................................................................................... 79
3.5 General Docking Connector Recommendations for Differential Interfaces .................. 80
4 System Memory Interface Design Guidelines ........................................................... 83
4 Intel Confidential CDI/IBP#: 543611
4.1 General Introduction ..........................................................................................83
4.1.1 Rules for Populating DIMM Slots ...............................................................83
4.2 Desktop - SKL-S UDIMM Guidelines......................................................................84
4.2.1 UDIMM Platform Stack-up ........................................................................85
4.2.2 UDIMM Platform Placement ......................................................................85
4.2.3 UDIMM Planes On Outer Layers (POOL) .....................................................85
4.2.4 UDIMM Connector High-Frequency Decoupling............................................86
4.2.5 UDIMM 2DPC T-Topology & Implementation Details.....................................86
4.2.6 UDIMM DDR3L/DDR4 Routing Guidelines ...................................................90
4.2.6.1 UDIMM Guideline Terminology.....................................................91
4.2.6.2 UDIMM Clock (CLK) Signal Group ................................................92
4.2.6.3 UDIMM Control (CTRL) Signal Group ............................................93
4.2.6.4 UDIMM Command (CMD) Signal Group.........................................94
4.2.6.5 UDIMM Data Signal Group ..........................................................96
4.2.6.6 UDIMM Miscellaneous Signals/Traces ...........................................98
4.2.6.7 UDIMM DDR3L/DDR4 Length and Matching Guidelines....................99
4.3 All-In-One - SKL-S SODIMM Guidelines............................................................... 101
4.3.1 SODIMM Platform ................................................................................. 101
4.3.1.1 AIO Via Pattern....................................................................... 101
4.3.1.2 SO-DIMM Connector High-Frequency Decoupling ......................... 103
4.3.2 SODIMM 2DPC DDR3L/DDR4 Routing Guidelines .......................................103
4.3.2.1 SODIMM 2DPC Guideline Terminology ........................................ 104
4.3.2.2 SO-DIMM 2DPC Clock (CLK) Signal Group...................................105
4.3.2.3 SO-DIMM 2DPC Control (CTRL) Signal Group .............................. 107
4.3.2.4 SO-DIMM 2DPC Command (CMD) Signal Group ........................... 108
4.3.2.5 SO-DIMM 2DPC Data Signal Group ............................................ 109
4.3.2.6 SO-DIMM Miscellaneous Signals/Traces ...................................... 111
4.3.2.7 SO-DIMM DDR3L/DDR4 Length and Matching Guidelines .............. 111
4.3.3 SODIMM 1DPC DDR3L/DDR4 Routing Guidelines .......................................113
4.4 System Memory Reference Voltage (VREF) Guidelines ..........................................119
5 DisplayPort* Design Guidelines..............................................................................121
5.1 DisplayPort* General Introduction ...................................................................... 121
5.1.1 DisplayPort* Bit Rates ...........................................................................121
5.1.2 DisplayPort* Main Link Buffer Type ......................................................... 122
5.1.3 Reference Documents............................................................................122
5.2 DisplayPort* Signal Descriptions ........................................................................ 122
5.2.1 Signal Groups ......................................................................................122
5.3 DisplayPort* Topology Guidelines.......................................................................123
5.3.1 Optimizations....................................................................................... 123
5.3.2 DisplayPort* Main Link Motherboard and Main Link Multiplexed Topologies ...124
5.3.3 DisplayPort* Auxiliary Channel Topologies................................................ 126
5.4 DisplayPort* General Considerations and Optimization ..........................................129
5.4.1 AUX-CH Stack-up Guidelines ..................................................................129
5.4.2 DisplayPort* HPD General Considerations and Optimization ........................ 129
5.4.3 DisplayPort* Main Link Differential-Pair Width and Spacing......................... 130
5.4.4 DisplayPort* Auxiliary Channel (AUX CH) General Design Considerations and
Optimization ........................................................................................ 130
5.5 DisplayPort* Length Matching Guidelines ............................................................132
5.6 Digital Display Interface Disabling and Termination Guidelines ............................... 132
5.7 Display Compensation Guidelines.......................................................................132
6 Embedded DisplayPort* (eDP*) Design Guidelines ................................................ 133
6.1 Embedded DisplayPort* (eDP*) Signal Descriptions .............................................. 133
6.2 Embedded DisplayPort* (eDP*) Topology Guidelines............................................. 134
6.3 Optimizations..................................................................................................134
CDI/IBP#: 543611 Intel Confidential 5
6.3.1 Skylake Processor Graphics Embedded DisplayPort* Main Link Topology for
HBR and HBR2..................................................................................... 135
6.3.2 DisplayPort* to VGA Topology ................................................................ 135
6.3.3 Skylake Processor Graphics eDP* Auxiliary Channel Topology..................... 136
6.3.4 Embedded DisplayPort* Hot-Plug Detect Implementation........................... 137
6.4 Embedded DisplayPort* Length Matching Guidelines ............................................ 137
6.5 Digital Display Interface Compensation Guidelines ............................................... 137
6.5.1 Embedded DisplayPort* Compensation Signal Routing Guidelines................ 138
6.5.2 eDP* Disabling and Termination Guidelines.............................................. 138
7 High-Definition Multimedia Interface* (HDMI*) Design Guidelines ....................... 139
7.1 Description..................................................................................................... 139
7.2 HDMI* Signal Description ................................................................................. 142
7.3 HDMI 1.4* Topology Guidelines......................................................................... 142
7.3.1 Differential-Pair Width and Spacing......................................................... 142
7.3.2 Optimizations ...................................................................................... 142
7.3.3 HDMI 1.4* Main Link Cost-reduced Level Shifter and Active Level Shifter
Topologies........................................................................................... 143
7.3.4 HDMI 1.4* (DDC) Signals Design Guidelines ............................................ 145
7.3.5 HDMI 1.4* DDC Signals on Motherboard Topologies with Cost-reduced Level
Shifter, Active Level Shifter and Docking Active Level Shifter...................... 146
7.3.6 HDMI 1.4* HPD Implementation............................................................. 147
7.4 HDMI* 2.0 Topology Guidelines......................................................................... 149
7.4.1 HDMI 2.0* HPD Implementation............................................................. 152
7.5 Digital Display Interface Disabling and Termination Guidelines............................... 152
7.6 Display Compensation Guidelines ...................................................................... 152
8 Processor - PCI Express* Design Guidelines .......................................................... 153
8.1 PCI Express* General Introduction..................................................................... 153
8.1.1 Description.......................................................................................... 153
8.1.2 Compliance Documents ......................................................................... 153
8.2 PCI Express* Signal Description ........................................................................ 153
8.3 PCI Express* Topology Guidelines ..................................................................... 154
8.3.1 PCI Express* Device Down Topologies..................................................... 154
8.3.2 PCI Express* Add-In Card Topology - SKL S ............................................ 155
8.4 PCI Express* General Routing Guidelines............................................................ 157
8.4.1 Reference Planes.................................................................................. 157
8.4.2 Lane to Controller Allocation .................................................................. 157
8.4.2.1 Static Lane Reversal Support.................................................... 158
8.5 PCI Express* Slot Reset Implementation ............................................................ 161
8.6 PCI Express* Debug Guidelines ......................................................................... 161
8.6.1 Probe Points for Testing Soldered Down PCI Express* Devices.................... 161
8.6.2 Desktop Form Factor Passive Components and Connectors......................... 162
8.6.2.1 Desktop Form Factor AC Coupling Capacitor Placement Guidelines. 162
8.6.2.2 Desktop Form Factor Connectors............................................... 163
8.6.3 AIO Form Factor Passive Components and Connectors............................... 164
8.6.3.1 AIO Form Factor AC Coupling Capacitor Placement Guidelines....... 164
8.6.3.2 AIO Form Factor Connectors..................................................... 165
8.7 PCI Express* Compensation Guidelines .............................................................. 165
9 Direct Media Interface Design Guidelines .............................................................. 167
9.1 DMI General Introduction ................................................................................. 167
9.1.1 Description.......................................................................................... 167
9.1.2 Compliance Specification ....................................................................... 167
9.2 DMI Signal Descriptions ................................................................................... 167
9.3 DMI Topology Guidelines .................................................................................. 167
