Gigabit Ethernet (GbE) Switch Subsystem User Guide.pdf

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This document gives a functional description of the Ethernet Switch Subsystem and related portions of the Serializer/Deserializer (SerDes) module. The Ethernet Switch Subsystem consists of the Ethernet Media Access Controller (EMAC) module, Serial Gigabit Media Independent Interface (SGMII) modules,
中 TEXAS NSTRUMENTS www.ti.com SPRUGV9D-June 2013 Release Date Description/Comments SPRUGV9C April 2013 Added additional port 3 and port 4 related register descriptions for Keystone ll.(Page 3-57) Added KS ll P2_ TS_CTL Field Descriptions. (Page 3-68) Added KS ll P2_TS_CTL Field Descriptions. (Page 3-61) Added Ks P2_TS_CTL Field Descriptions (Page 3-54) Added KS ll P1_TS_CTL Field Descriptions.(Page 3-47 Add Keystone l Overrun Type ll in Architecture .(Page 2-17 Added extra ports for STATSB for Key Stone lI devices. (Page 2-19 Added Key Stone Il Overrun Type 2 in registers. (Page 2-18 Added Key Stone II port enable in registers.( Page 3-36) Added Key Stone Il Reset Considerations in Arch. ( Page 2-53 Added Keystone ll SerDes Architecture section in Architecture chapter. (Page 2-53 Added Keystone ll specifics in Introduction. (Page 1-4) Added Key stone ll statistics submodule in architecture. (Page 2-13) Added Key Stone ll Time Sync Event Field. (Page 2-28) Added Key Stone II Time Synchronization Submodule Architecture section.(Page 2-25) Added Key Stone lI Type 3 Overrun Registers. (Page 2-19) Added Port 3 and Port 4 Interfaces note in arch.(Page 2-27 Added port 3 and port 4 MAC in Initialization for Keystone ll.(Page 2-54 Added ports to Type 2 Key Stone I Register for Keystone ll. (Page 2-18 Added STATSC and STATSD module details in Overrun Type 1.(Page 219) Additional Key Stone ll detail added to Switch Architecture. (Page 2-4) Added EVENT_MID register description. (Page 3-101 Added Key Stone ll CPTS Memory Map.( Page 3-96 Added Keystone ll Port O Source ID Register. (Page 3-40)age Added Key Stone lI FLOW_CONTROL Register Description. (Page 3-39 Added Keystone lI PTYPE Register.(Page 3-37 Added noted about Keystone l devices Register field descriptions. ( Page 3-55) Corrected Address in Memory Map. (Page 3-4) Corrected Register Addresses in Memory Map. (Page 3-10) Corrected Register Addresses in Memory Map. (Page 3-10) Corrected Register Addresses in Memory Map. ( Page 3-10) Added Keystone ll Features in Features list.(Page 1-2 SPRUGV9B July 2012 Updated addresses for port 1 MAC registers in GbE switch complete register listing table. ( Page 3-9) Updated addresses for port 1 MAC registers in GbE switch complete register listing table. (Page 3-4) Updated the description for the SGMll SerDes LOoP_BWIDTH field. (Page 3-116 Updated the field description for the no_learn bit in the ale port Control Register 0.(Page 3-109 Updated the field description for the SGMll Ser Des RATE field. ( Page 3-118) Updated the recommended settings for the SGMll SerDes EQ field description. (Page 3-118) Modified procedure description for SGMll to SGMII with Forced Link step 1b. (Page 2-49 SPRUGV9D-June 2013 Key Stone Architecture Gigabit Ethernet(GbE) Switch Subsystem User Guide 0-s Submit Documentation Feedback 中 EXAS Ⅰ NSTRUMENTS www.ti.com Release Date Description/Comments SPRUGV9A July 2011 Modified the field description tables so they include all field labels shown in the related register figure and their corresponding bit numbers. ( Page 3-1 Added Gigabit Ethernet Switch Subsystem Descriptor Error Flags table. ( Page 2-42 Added Ratescale values table.(Page 3-116 Added SGMIl_ SERDES_ STS Register. (Page 3-114 Changed Start of Frame statistic to Overrun Type 3 statistic and updated the description (Page 2-19) Changed Start of Frame statistic to Overrun Type 2 statistic and updated the description. ( Page 2-18) Changed Start of Frame statistic to Overrun type 1 statistic and updated the description. ( Page 2-17) Updated SerDes SGMIl Boot Configuration Registers to add SGMIl_SERDES_STS register. Page 3-114 Updated VRANGE field description in the SGMIl PLL Configuration Register. ( Page 3-116) Updated procedure for setting up the SGMll in master mode with autonegotiation. (Page 2-48 Updated procedure for setting up the SGMIl in slave mode with autonegotiation. (Page 2-48) Updated the SGMIl to SGMIl with forced link procedure from 0x21 to 0x21. (Page 2-49 Updated the Time Synchronization Submodule Architecture. ( Page 2-25) Added Ethernet Switch Subsystem Complete Register Listing Table. (Page 3-2) Changed RF TCLK_ SEL to CPTS_RTFCLK_ SEL.(Page 2-33 Changed RTFCLK_SEL to CPTS_RTFCLK_SEL. (Page 2-2) Changed RTFCLK_SEL[4: 0] to CPTS_RTFCLK_SEL[2: 0]. (Page 2-2 SPRUGV9 November Initial release KeyStone Architecture Gigabit Ethernet(GbE) Switch Subsystem User Guide SPRUGV9D-une 2013 Submit documentation feedback XA INSTRUMENTS www.ti.com Contents Contents Release History. List of tables List of Fiqure ·· .,.¢-XV List of procedur Prefa 0-XIX about this manual ,,,,,,,,,,,,,,,,,,.,,,-XX Notational Conventions. Related docu tation from texas instruments Trademarks ·············:·· ,,,,,,,,,.OXX Chapter 1 Introduction 1.1 Purpose of the peripheral ··.·:·::· 1.2 Features 看音 1-2 1.3 Gigabit Ethernet Switch Subsystem Functional Block Diagram ·垂 1.4 Industry Standard(s)Compliance Statement 1-5 Chapter 2 Architecture 2-1 2.1 Clock Control 2-2 2.1.1 Gigabit Switch Subsystem Clock .2-2 2.1.2 SGMll SerDes reference clock 2-2 2.1.3 MDIO Clock .2-2 2.1.4 IEEE 1588 Time Synchronization Clock 2-2 2.1.5 GMll Clock 2.2 Memory Map...........,....,.......... ··········· 2-3 2. 3 Gigabit Ethernet Switch Architecture 2-4 2.3.1 Streaming Packet Interface 2.3.1.1 Transmit Streaming Packet Interface · ;···:···.···· 2-5 2.3.1.2 Transmit VLAN Processing.... 2-5 2.3.1.3 Receive Streaming Packet Interface................... 2-5 23.2 Media access Controller submodule architecture 2.3.2.1 Data Receive operations .2-7 2.3.2.2 Data Transmission 29 23. 3 MAC Receive fifo architecture 2-12 23.4 Statistics submodule architecture 2-13 2.3.4.1 Accessing Statistics Registers 2.3.4.2 Statistics Interrupts ∴..2-14 2.3.4.3 Receive statistics Descriptions 2-14 2.3. 4.4 Transmit(Only) Statistics Descriptions ∴.2-20 2.3.4.5 Receive and Transmit(Shared)Statistics Descriptions 2-23 2.3.5 Time Synchronization Submodule Architecture 2.3.5.1 KeyStone ll Time Synchronization Submodule Architecture 2-2 2.3.5.2 Time Synchronization Submodule Components.......... ∴.2-26 2.3.5.3 Time Synchronization Events 2-27 2.3.5. 4 Time Synch tion initialization 2-33 2.3.5.5 Detecting and Processing Time Synchronization Events 2-33 2.3.6 Address Lookup Engine(ALE)Submodule Architecture 2-34 2,3.6.1 ALE Tabl 2-35 2.3.6.2 Reading Entries from the ALe Table ∴.2-36 SPRUGV9D-June 2013 KeyStone Architecture Gigabit Ethernet (GbE)Switch Subsystem User Guide Submit documentation Feedback TEXAS INSTRUMENTS Contents www.tl.com 2.3.6. 3 Writing Entries to the ALE Table ∴∴2-36 2.3.6.4 ALE Table Entry Types 2-36 2.3.6.5 ALE Packet Forwarding Process .2-41 2.3.6.6 ALE Learning process 2-45 2.4 Serial Gigabit Media Independent Interface(SGMII)Architecture............... 2-46 24.1 SGMII Receive Interface 2-46 2.4.2 SGMII Transmit Interface 2-46 2.4.3 Modes of operatior 2-46 2.4.3.1 Digital Loopback 2-46 2.4.3.2 SGMII to PHY Configurat 2-47 2.4.3.3 SGMII to SGMl with Autonegotiation Configuration 2-48 24.34SGM! tO SGMIl with Forced Link Configuration..……,,,…,,…,2-49 2.5 Management Data Input 2.5. 1 Global PHY Detection and Link State Monitoring ∴.2-50 2.5.2 PHY Register User Access ,2-50 2.5.2.1 Writing Data to a PHY Register 2-51 2.5.2.2 Reading Data from a PHY Register 2.5.3 MDIO Interrupts ∴2-51 2.5.3.1 MDIO Link Status Interrupts. 2-52 2.5.3.2 MDIO User Access Interrupts 2-52 2.5.4 Initializing the MDIO Module ∴.2-52 2.6 Key stone I Serializer/Deserializer (serDes) Architecture .2-52 2.7 KeyStone ll Serializer/Deserializer (SerDes) Architecture 2-53 2. 8 Reset considerations .2-53 2.9 Initialization 2-54 2.10 Interrupt Support..…,,…,,,…,,,…,,,,…,,,,,,…,,…,2-54 2.10.1 Interrupt Events 2-54 2.11 Power Management,,,,,,,,,…… .,2-54 Chapter 3 Registers 3.1 Summary of Modules ...,....... ,3-2 3.2 Gigabit Ethernet(gbE)Switch Subsystem Module ,,3-15 3.2.1 Ethernet Switch Subsystem Identification and Version Register(ES_Ss_IDVER 3-15 3. 3 Serial Gigabit Media Ind nt Interface (sgml)module 3-16 3.3. 1 SGMII ldentification and version Register(SGMII_IDVER) ,3-17 3. 2 Software Reset Register(SOFT_RESET) 3-17 6.3.3 SGMII Control Register(SGMIL_CONTrOl 3-18 3.3.4 Status Register(STATUS) 3-18 3.3.5 Advertised ability Register(MR_ ADV_ABILITY) 3-19 335.1 SGMII MODE 3-19 3.3.6 Link Partner Advertised ability Register(MR_LP_ADV_ABILITY) 3-20 3.4 Management Data Input/Output(MDIO)module ∴3-21 34.1 MDIO Version re (MDIO VERSION) 3-21 3.4.2 MDIO Control Register(MDIO CONTROL) 3-22 3.4.3 PHY Alive Status Register (ALIVE) 3-23 3.4, 4 PHY Link Status Register(LINK)......... 3-23 3.4.5 MDIO Link Status Change Interrupt(Unmasked )Register(LINKINTRAW) .3-24 3.4.6 MDIO Link Status Change Interrupt(Masked) Register(LINKINTMASKED) 3-24 3.4.7 MDIO User Command Complete Interrupt(Unmasked) Register(USERINTRAW) 3-25 3.4.8 MDIO User Command Complete Interrupt(Masked )Register(USERINTMASKED) 3.4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSE 3-25 3.4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAr)....... 3-26 3.4.11 MDIO User Access register o (USERACCESSO 3.4. 12 MDIO User PHY Select Register O (USERPHYSELO ,3-27 3.4.13 MDIO User Access Register 1(USERACCESS1) Key Stone Architecture Gigabit Ethernet(GbE) Switch Subsystem User Guide SPRUGV9D-June 2013 Submit documentation Feedback eXAS INSTRUMENTS Contents www.tl.com 3.4. 14 MDIO User PHY Select Register 1(USERPHYSEL1) 3-28 3.5 Ethernet switch module 3-30 3.5.1 Gigabit Ethernet(GbE)Switch Submodule 3-30 3.5.1.1 GbE Switch Identification and Version Register(CPSW_IDVER 333 3.5.1.2 GbE Switch Control Register(CPSW_CONTROL) 34 3.5.1.3 Emulation Control Register(Em_ CONtRol) 3-35 3.5.1.4 Statistics Port Enable (STAT PORt en) 3.5.1.5 Priority Type Register(PTYPE)...... 3-37 3.5.1.6 Key Stone I and Key stone lI MAC Short Gap Threshold Register(GAP__THRESH) 3.5. 1.7 Transmit FIFO Start Words Register (TX_START_WDS) 3.5. 1.8 Flow Control Register(FLOW_CONTROl 3-39 3.5.1.9 Port O Source Identification Register(PO_CPPL_SRC_ID)...................3-39 3.5.1.10 Port O VLAN Register(PO_PORT_VLAn) .,3-40 3.5.1.11 Port 0 Receive Packet Priority to Header Priority Mapping Register(PO_RX_PRI_MAP)... 3-41 3.5.1. 12 Porto Receive Maximum Length register(PoRX_maXlen) ∴.,3-42 3.5.1. 13 Port 1 Max Blocks Register(P1_MAX_BLKS 3-42 3.5.1.14 Port 1 Block Count Register(P1_BLK_CNt) 3-43 3.5.1. 15 Port 1 VLAN Register (P1_ PORT_VLAN) ······· 3-43 3.5.1.16 Port 1 Transmit Header Priority to Switch Priority Mapping Register(P1_TX_PRI_MAP)....3-44 35.1.17MAC1 Source Address Low Register(MAC1_SALO)………………………………3-45 3.5.1.18 MACI Source Address High register(MAC1 SA hi 3-45 3.5. 1.19 Port 1 Time Sync Control Register(P1_TS_CTL 3-46 3.5.1.20 Port 1 Time Sync Sequence ID and LTYPE Register(P1_TS_ SEQ_LTYPE ∴3-47 3.5.1.21 Port 1 Time Sync Control Register 2(P1_TS_CTL2 ∴3-48 3.5. 1.22 Port 1 Time Sync Control Register and LTYPE2(P1_TS_CTL_LTYPE2 3-48 3.5. 1.23 Port 1 Time Sync VLAN LTYPE Register(P1_TS_VLAN_LTYPE) ……∴∴3-49 3.5.1. 24 Port 2 Max blocks Register(P2_MAX_BLKS). .3-50 3.5.1.25 Port 2 Block Count Register(P2_BLK_CNt) 3-50 3.5.1.26 Port 2 VLAN Register(P2_PORT_VLAN) 3-51 3.5.1.27 Port 2 Transmit Header Priority to Switch Priority Mapping Register(P2_TX_PRI_MAP)....3-51 35.1.28MAC2 Source Address Low Register(MAC2SALO)……………352 3.5.1. 29 MAC2 Source Address High Reserved Register(MAC2_SA_HI) 3-53 3.5.1.30 Port 2 Time Sync Control Register(P2_ TS_ CTL) 3-53 3.5.1.31 Port 2 Time Sync Sequence id and LTYPE Register(P2_TS SEQ LTYPE) 3.5.1.32Pot2 Time Sync VLAn LTYPE Register(P2_TSⅥ LAN LTYPE)..……3-55 3.5. 1.33 Port 2 Time Sync Control Register 2(P2_TS_CTL2 3.5.1.34 Port 2 Time Sync Control Register and LTYPE2(P2_TS_CTL_LTYPE2 3-56 3.5.2 Keystone ll Port 3&4 Re Descrip 3-57 3.5.2.1 Port 3 Max Blocks Register(P3_MAX_BLKS) ∴.,3-57 3.5.2.2 Port 3 Block Count Register(P3_BLK_CNT) 3.5.2.3 Port 3 VLAN Register(P3_PORT_VLAN) 3-58 3.5. 2 4 port 3 Transmit header Priority to Switch Priority mapping register(p3_TX_PRl MaP)....3-59 3.5. 2.5 MAC3 Source Address Low Register(MAC3 SA_LO) 3.5.2.6 MAC3 Source Address High Register(MAC3_ SA_H 3-60 3.5.2.7 Port 3 Time Sy oI Register (P3_TS_ctL 3.5.2.8 Port 3 Time Sync Sequence ID and LTYPE Register(P3_TS_SEQ_LTYPE 3-62 3.5.2.9 Port 3 Time SynC VLAn LTYPE Register(P3 TS VLAN_ LTYPE 单·面 3.5.2.10 Port 3 Time Sync Control and LTYPE2 Register(P3TS_CTLLTYPE2)............3-63 3.5.2.11 Port 3 Time Sync Control Register 2(P3_TS_CTL2) ∴3-64 3.5. 2.12 Port 4 Max Blocks Register(P4_MAX_BLKS 3-64 3.5.2. 13 Port 4 Block Count Register(P4 BLK Cnt) 3-65 3.5.2. 14 Port 4 VLAN Register(P4_PORT_VLAN) 3.5.2. 15 Port 4 Transmit Header Priority to Switch Priority Mapping register(p4_TX_PRI_MAP 3-66 3.5.2.16 MAC4 Source Address low Register(MAC4_SA_LO) ...3-67 3.5.2.17 MAC4 Source Address high register (Mac4 SA hi) 3-67 3.5.2.18 Port 4 Time Sync Control Register(P4_TS_CTL)........ ∴.3-68 3.5.2. 19 Port 4 Time Sync Sequence ID and LTYPE Register (P4_TS_ SEQ_LTYPE)...........3-68 3.5.2. 20 Port 4 Time SynC VLAN LTYPE Register(P4_TS_VLAN_LTYPE 3-69 3.5.2.21 Port 4 Time Sync Control Register and LTYPE2(P4_TS_CTL_LTYPE2)............3-69 PRUGV9D-une 2013 Keystone Architecture Gigabit Ethernet(GbE) Switch Subsystem User Guide 0-vil Submit documentation Feedback TEXAS INSTRUMENTS Contents www.tl.com 3.5. 2.22 Port 4 Time Sync Control Register 2(P4_TS_CTL2 3.5.3 Ethernet Media access Controller(EMAo Submodule 3.5.3.1 MAC Identification and version Register(MAC_IDVER .3-72 3.5.3.2 MAC Control Register(MAC_CONTROL) 3-72 3.5.3.3 MAC Status Register(MACSTaTUs). .3-74 3.5.3.4 Software Reset Register(SOFT_ RESET) ∴.3-75 3.5.3.5 Receive Maximum Length Register(RX_MAXLen). ...........................................3-75 353.6 Receive pause Timer Register(RX_ PAUSE).…,,…,,…,… 3.5. 3.7 Transmit Pause Timer Register (TX PAUSe 3-76 3.5.3.8 Emulation Control Register(EM_CONT 3-76 3.5.3.9 Receive Packet Priority to Header Priority Mapping Register(MAC_RX_PRL_MAP 3-77 3.5.4 Statistics (STATS) Submod 3-78 6.5.4.1 Good Receive Frames Register(RXGOODFRAMES 3-79 3.5.4.2 Broadcast Receive Frames Register(RXBROADCASTFRAMES .3-79 3.5.4.3 Multicast Receive Frames Register( RXMULTICASTFRAMES) 380 3.5.4.4 Pause Receive Frames Register(RXPAUSEFRAMES 3.5. 4.5 Receive CRC Errors Register(rXCrCerrors ∴.,3-81 3.5.46 Receive Align/Code Errors Register(RXALIGNCODEERRORS 3-81 3.5.4.7 Oversize receive frames register ( rXoversizedframes) 3-82 3.5.4. 8 Receive Jabber Frames Register(RXJABBERFRAMES 3-82 3.5.4.9 Undersize(short)Receive Frames Register(RXUNdERSIZEDFRAMES) 3.5.4.10 Receive Fragment Register(RXFRAGmENtS) 3.5. 4.11 Receive Octets register(RXOCTETs 3-84 3.5.4.12 Good Transmit Frames Register (TXGOODFRAMES).....................3-84 3.5.4. 13 Broadcast Transmit Frames Register(TXBROADCASTFRAMES ∴.3-85 3.5. 4.14 Multicast Transmit Frames(TXMULTICASTFRAMES) 垂· ..3-85 3.5.4.15 Pause Transmit Frames Register (TXPAUSEFRAMES 3-86 3.5.4.16 Deferred Transmit Frames register ( tXdEFERREdFrames .3-86 3.5.4.17 Transmit Frames Collision Register tXcolliSIONFRAmeS 3-87 3.5.4.18 Transmit Frames Single Collision Register(TXSINGLECOLLF RAMES) 3-87 3.5.4.19 Transmit Frames Multiple Collision Register (TXMULTCOLLFRAMES 3.5. 4.20 Transmit Excessive Collision Register (TXEXCESSIVECOLLISIONS 3-88 3.5.4.21 Transmit Late Collisions Register(TXLATECOLLISIONS 3.5. 4.22 Transmit Frames Underrun register (tXUnderrun)...........,......,..3-89 3.5.4.23 Transmit Carrier Sense Errors Register (TXCarriersenseerrors 3.5.4.24 Transmit Octets Register (TXOCTETS) 垂着 3.5.4. 25 Receive and transmit 64 Octet Frames Register(640CTETFRAMES) 3-91 3.5.4.26 Receive and Transmit 65-127 Octet Frames Register (65T1270CTETFRAMES) 3.5.4.27 Receive and Transmit 128-255 Octet Frames Register(128T255OCTETFRAMES) ...3-92 3.5.4.29 Receive and Transmit 512-1023 Octet Frames Register(512T10230CTETFRAMES\,....3-92 3.5.4.28 Receive and Transmit 256-511 Octet Frames register (256T511OCTETFRAMes) 3-93 3.5. 4.30 Receive and Transmit 1024 and Up Octet Frames Register (1024TUPOCTETFRAMES) .........3-93 3.5. 4.31 Net Octets Register(NEtoCTEts 3-94 3.5. 4.32 Receive Start of Frame Overruns Register (rXSoFoverruns 3-94 3.5. 4.33 Receive middle of frame Overruns Register (RXMOFOVERRUNS 395 3.5.4.34 Receive DMA Overruns Register(RXDMAOVERRUNS).......... 3.5.5 Time Synchronization( CPTS) submodule 3-96 3.5.5.1 CPTS Identification and Version Register(CPTS_IDVER 3-97 3.5.5.2 Time Sync Control Register(TS_CTL) 3.5.5.3 RFTCLK Select Register(CPTS_RFTCLK_SEL)................... 3-98 3.5.5.4 Time Stamp Event Push Register(TS_PUSH) 3.5.5.5 Interrupt Status Raw Register(INTSTAT_RAW)........................3-99 3.5.5.6 Interrupt Status Masked Register(INTSTAT_MASKED) 3-99 3.5.5.7 Interrupt Enable Register(INT ENABLE 3.5.5.8 Event Pop Register(EVENT_POP) ,,3-100 3.5.5.9 Event Low Register (event low ....3-100 3.5.5.10 Event Middle Register (EVENT_MID) 3-101 3.5.5.11 Event High Register(EVENT_HIGH) ∴,3-101 3.5.6 Address Lookup Engine(ALE)submodule 3-103 Key Stone Architecture Gigabit Ethernet(GbE) Switch Subsystem User Guide SPRUGV9 D-June 2013 Submit dour Ition Feedback eXAS INSTRUMENTS Contents www.tl.com 3.5.6.1 ALE Identification and version Register(ALE_IDvEr ∴,.3-104 3.5.6.2 ALE Control Register (ALE_CONTROL ...3-104 3.5.6.3 ALE Prescale Register (ALE_PRESCAle 3-105 3.5.6. 4 ALE Unknown VLAN Register(UNKNOWN_VLAN) 3.5.6.5 ALE Table Control Register(ALE_TBLCTL) ,3-107 3.5.6.6 ALE Table Word 2 Register (ALE_TBLW2).......................... 3-107 3.5.6.7 ALE Table Word 1 Register (ALE_TBLW1) 3-108 3.5.6. 8 ALE Table Word o Register (Ale_ tBlwo 3.5.6.9 ALE Port 0 Control Register (ALE PORTCTLO 3-108 3.5.6.10 ALE Port 1 Control Register(ALE_POrtctl1) .·····..·· ∴,.3-109 3.5.6.11 ALE Port 2 Control Register(ALE_ PORTCTL2 3-110 3.5.6.12 ALE Port 3 Control Register (ALE_PORTCTL3 3-111 3.5.6.13 ALE Port 4 Control Register(ALE_ PORTCTL4)....... 3.5.6.14 ALE Port 5 Control Register(ALE_PORTCTL5)..................... 3-112 3.6 Serializer/Deserializer (Ser Des) SGMll Boot Configuration Registers. ........................3-114 3.6. 1 SGMII SerDes Status Register(SGMII_ SERDES STS ,,3-114 3.6.2 SGMII PLL Configuration Register (SGMIl_ SERDES_CFGPLl) ………3-115 3.6. 3 SGMII Receive Configuration Register n(SGMII_ SERDES_CFGRXn) 3-117 3.6.4 SGMII Transmit Configuration Register n(SGMIl_SERDES_CFGTXn 3-120 SPRUGV9D-June 2013 KeyStone Architecture Gigabit Ethernet(GbE) Switch Subsystem User Guide Submit documentation Feedback TEXAS INSTRUMENTS List of tables www.tl.com List of tables Key Stone ll Gigabit Ethernet Switch Subsystem Mod∴…… Table 2-1 KeyStone I Gigabit Ethernet Switch Subsystem Modules 2-3 Table 2-2 2-3 Table 2-3 Keystone I Ps Flags for GbE Switch Ingress Packets 2-6 Table 2-4 Key Stone ll PS_FLAGS for GbE Switch Ingress Packets..............................2-6 Table 2-5 Keystone I Time Synchronization Event Field ∴,2-28 Table 2-6 Key stone ll Time Synchronization event Fields 2-28 Table 2-7 ALE Table learned address Control bits ∴2-35 Table 2-8 Free Table Entry Field Configuration 2-37 Table 2-9 Multicast Address Table Entry Field Configuration ∴..2-37 Table 2-10 VLAN/Multicast Address Table Entry Field Configuration ∴.2-37 Table 2-11 Unicast Address Table Entry Field Configuration ∴2-38 Table 2-12 OUI Unicast Address table Entry Field Configuration 2-38 Table 2-13 VLAN/Unicast Table Entry Field Configuration 2-39 Table 2-14 VLAN Table Entry Field Configuration 2-39 Table 2-15 ALE Table Entry Field Descriptions........... 2-40 Table 2-16 Gigabit Ethernet Switch Subsystem Descriptor Error Flags 2-42 Table 2-17 ALE Ingress Filtering Process ∴.,.2-42 Table 2-18 VLAN Aware Lookup Process 垂·1 2-43 Table 2-19 VLAN Unaware Lookup Process 2-44 Table 2-20 ALE Egress Process ∴.2-44 Table 2-21 ALE Learning Process .2-45 Table 3-1 Key stone I Gigabit Ethernet Switch Subsystem Modules 3-2 Table 3-2 KeyStone ll Gigabit Ethernet Switch Subsystem Module 3-2 Table 3-3 KeyStone I Gigabit Ethernet Switch Subsystem Complete Register Listing 3-2 Table 3-4 Key Stone ll Gigabit Ethernet Switch Subsystem Complete Register Listing ∴,3-7 Table3-5 Ethernet switch Subsystem Module 3-15 Table 3-6 Ethernet Switch Subsystem Identification and Version Register(ES_SS_IDVER) Field Descriptions 3-15 Table 3-7 gMll Registers. 3-16 Table 3-8 SGMII ldentification and version Register(SgML_IDVER) Field Descriptions 3-17 Table 3-9 Software Reset Register(SOFT_RESET) Field Descriptions. .......................................................3-17 Table 3-10 SGMIl Control Register(SGMI_CONTROL)Field Descriptions 3-18 Table 3-11 Status Register(STATUS)Field Descriptions ∴3-18 Table 3-12 Advertised Ability Register(MR_ADV_ABILITY) Field Descriptions ............ 3-19 Tabe3-14 Link Partner Advertised Ability Register( MR LP AD∨ ABILITY Field Descriptions……,…………………3-19 Table 3-13 Advertised Ability and Link Partner Advertised Ability for SGMll Mode Table 3-15 MDIO Registers 3-21 Table 3-16 MDIO Version Register(MDIO_VERSION) Field Descriptions 3-22 Table 3-17 MDIO Control Register(MDIO CONTROL) Field Descriptions. 3-22 Table 3-18 PHY Alive Status Register Field Descriptions 3-23 Table 3-19 PHY Link Status Register(LINK)Field Descriptions 3-23 Table 3-20 MDIO Link Status Change Interrupt (Unmasked) Register(LINKINTRAW) Field Descriptions ..3-24 Table 3-21 MDIO Link Status Change Interrupt(Masked) Register(LINKINTMASKED) Field Descriptions ,.3-24 Table 3-22 MDIO User Command Complete Interrupt(Unmasked) Register(USERINTRAW) Field Descriptions 3-25 Table 3-23 MDIO User Command Complete Interrupt(Masked ) Register(USERINTMASKED) Field Descriptions 3-25 Table 3-24 MDIO User Command Complete Interrupt Mask Set Register(USERINTMASKSET) Field Descriptions 3-26 Table 3-25 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Descriptions 3-26 Table 3-26 MDIO User Access register 0(USERACCESSO) Field Description .3-27 Table 3-27 MDIO User PHY Select Register 0(USERPHYSELO) Field Descripti Tabe3-28 MDIO User Access Register7( USERACCESS1) Field Description s.,……………,3-27 3-28 Table 3-29 MDIO User PHY Select Register 1(USERPHYSEL1)Field Descriptions. 3-28 Table 3-30 Key Stone I Ethernet Switch Submodules 3-30 Table 3-31 Key stone ll Ethernet Switch Submodules 3-30 0-X Key stone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide SPRUGV9D-June 2013 Submit documentation Feedback

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