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/** ****************************************************************************** * @file stm32f0xx_rcc.c * @author MCD Application Team * @version V1.2.1 * @date 22-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Reset and clock control (RCC) peripheral: * + Internal/external clocks, PLL, CSS and MCO configuration * + System, AHB and APB busses clocks configuration * + Peripheral clocks configuration * + Interrupts and flags management * @verbatim =============================================================================== ##### RCC specific features ##### =============================================================================== [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS, all peripherals are off except internal SRAM, Flash and SWD. (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses; all peripherals mapped on these busses are running at HSI speed. (#) The clock for all peripherals is switched off, except the SRAM and FLASH. (#) All GPIOs are in input floating state, except the SWD pins which are assigned to be used for debug purpose. [..] Once the device started from reset, the user application has to: (#) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (#) Configure the System clock frequency and Flash settings (#) Configure the AHB and APB busses prescalers (#) Enable the clock for the peripheral(s) to be used (#) Configure the clock source(s) for peripherals which clocks are not derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG) @endverbatim ****************************************************************************** * @attention * * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_rcc.h" #include "stm32f0xx.h" /** @addtogroup STM32F0xx_StdPeriph_Driver * @{ */ /** @defgroup RCC * @brief RCC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ---------------------- RCC registers mask -------------------------------- */ /* RCC Flag Mask */ #define FLAG_MASK ((uint8_t)0x1F) /* CR register byte 2 (Bits[23:16]) base address */ #define CR_BYTE2_ADDRESS ((uint32_t)0x40021002) /* CFGR register byte 3 (Bits[31:23]) base address */ #define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007) /* CIR register byte 1 (Bits[15:8]) base address */ #define CIR_BYTE1_ADDRESS ((uint32_t)0x40021009) /* CIR register byte 2 (Bits[23:16]) base address */ #define CIR_BYTE2_ADDRESS ((uint32_t)0x4002100A) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup RCC_Private_Functions * @{ */ /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions * @brief Internal and external clocks, PLL, CSS and MCO configuration functions * @verbatim =============================================================================== ##### Internal-external clocks, PLL, CSS and MCO configuration functions ##### =============================================================================== [..] This section provides functions allowing to configure the internal/external clocks, PLL, CSS and MCO. (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through the PLL as System clock source. The HSI clock can be used also to clock the USART, I2C and CEC peripherals. (#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock the ADC peripheral. (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC clock source. (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. LSE can be used also to clock the USART and CEC peripherals. (#) PLL (clocked by HSI or HSE), for System clock. (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs (HSE used directly or through PLL as System clock source), the System clock is automatically switched to HSI and an interrupt is generated if enabled. The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, LSI, HSE, LSE or PLL (divided by 2) clock on PA8 pin. @endverbatim * @{ */ /** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * @note HSI ON and used as system clock source * @note HSI14, HSE and PLL OFF * @note AHB, APB prescaler set to 1. * @note CSS and MCO OFF * @note All interrupts disabled * @note However, this function doesn't modify the configuration of the * @note Peripheral clocks * @note LSI, LSE and RTC clocks * @param None * @retval None */ void RCC_DeInit(void) { /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; #if defined (STM32F0XX_MD) /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ RCC->CFGR &= (uint32_t)0xF8FFB80C; #else /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ RCC->CFGR &= (uint32_t)0x08FFB80C; #endif /* STM32F0XX_MD */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ RCC->CFGR &= (uint32_t)0xFFC0FFFF; /* Reset PREDIV1[3:0] bits */ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; /* Reset HSI14 bit */ RCC->CR2 &= (uint32_t)0xFFFFFFFE; /* Disable all interrupts */ RCC->CIR = 0x00000000; } /** * @brief Configures the External High Speed oscillator (HSE). * @note After enabling the HSE (RCC