FPGA51内核，利用Verilog编写_fpga实现51内核资源-CSDN文库

共26个文件

jpg：5个

v：4个

bsf：3个

FPGA

Verilog

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89c51ipcore.rar （26个子文件）

89c51ipcore

mc8951_ram_wave0.jpg 103KB

mc8051_rom_waveforms.html 1KB

mc8951_ramx_wave0.jpg 103KB

89c51.qws 152B

mc8951_ram_waveforms.html 2KB

mc8951_ram_wave1.jpg 127KB

mc8951_ram.bsf 4KB

rom_1.mif 56KB

89c51.eco.cdb 161B

89c51.db_info 137B

89c51.sld_design_entry.sci 154B

mc8051_rom.bsf 3KB

mc8051_rom.vhd 6KB

mc8051_rom.cmp 969B

mc8951_ram_bb.v 5KB

mc8051_rom_wave0.jpg 103KB

mc8951_ramx_waveforms.html 2KB

mc8951_ramx.bsf 4KB

mc8951_ramx_bb.v 6KB

mc8951_ramx.cmp 1KB

mc8951_ramx.v 7KB

mc8951_ramx_wave1.jpg 128KB

89c51.qsf 2KB

mc8951_ram.v 7KB

mc8951_ram.cmp 1KB

89c51.qpf 908B

<html> <head> <title>Sample Waveforms for mc8951_ramx.v </title> </head> <body> <h2><CENTER>Sample behavioral waveforms for design file mc8951_ramx.v </CENTER></h2> The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design mc8951_ramx.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design mc8951_ramx.v has one read/write port. The read/write port has 2048 words of 8 bits each. The core uses a different clock enable than the input registers. The output of the read/write port is unregistered. <CENTER><img src=mc8951_ramx_wave0.jpg> </CENTER> <CENTER>Fig. 1 : Wave showing read operation. </CENTER> The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. <CENTER><img src=mc8951_ramx_wave1.jpg> </CENTER> <CENTER>Fig. 2 : Waveform showing write operation </CENTER> The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. Actual write into the RAM happens at the falling edge of the write clock. The clock enable on the write side input registers are disabled. During a write cycle, the new data flows through to the output. </body> </html>

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