LPC2368学习资料资源-CSDN下载

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### LPC2368 学习资料：深入解析与应用 #### 一、LPC2368微控制器概述 LPC2368微控制器系列（包括LPC2364/65/66/67/68）是基于ARM7TDMI-S CPU的高性能嵌入式设备，其独特的架构结合了实时仿真功能，同时内置高达512kB的高速闪存。这款微控制器拥有一个128位宽内存接口以及专有的加速器架构，使得在最大时钟速率下能够高效执行32位代码。在中断服务例程和数字信号处理（DSP）算法等关键性能场景下，其性能比Thumb模式提高了30%以上，而在代码大小敏感的应用中，16位Thumb模式可减少超过30%的代码量，同时保持最小的性能损失。 #### 二、通信与控制特性 LPC2368系列特别适合多用途串行通信应用，集成了丰富的通信接口，如10/100 Ethernet MAC、USB全速设备（带4kB端点RAM，仅限LPC2364/66/68）、四个UART、两个CAN通道（仅限LPC2364/66/68）、SPI接口、两个SSP、三个I2C接口以及I2S接口。此外，内部配备的4MHz振荡器、最高32kB的SRAM、用于Ethernet的16kB SRAM、用于USB及通用目的的8kB SRAM，以及2kB电池供电SRAM，使其成为通信网关和协议转换器的理想选择。丰富的32位定时器、10位ADC、10位DAC、PWM单元、CAN控制单元（仅限LPC2364/66/68），以及多达70个快速GPIO线，最多支持12个边缘或电平触发的外部中断引脚，使这些微控制器在工业控制和医疗系统中表现出色。 #### 三、特色功能与优势 1. **ARM7TDMI-S处理器**：最高运行频率达72MHz，为复杂任务提供强大的计算能力。 2. **片上大容量闪存**：提供最高512kB的闪存程序存储空间，支持In-System Programming (ISP)和In-Application Programming (IAP)，确保灵活的编程和更新能力。 3. **高速SRAM**：8kB至32kB的SRAM位于ARM本地总线上，优化了CPU访问速度，提高了整体性能。 4. **专用SRAM**：为Ethernet和USB提供了额外的SRAM，增强了数据传输效率。 5. **双AHB系统**：实现Ethernet DMA、USB DMA与片上闪存程序执行的同时进行，无功能竞争，提升了多任务处理能力。 6. **高级外围设备**：包括高精度ADC、DAC、PWM单元、CAN控制单元等，适用于各种精密测量和控制需求。 7. **丰富的GPIO与中断管理**：提供了大量的GPIO引脚和中断管理机制，支持复杂的输入/输出操作。 #### 四、应用场景 LPC2368系列微控制器凭借其卓越的性能和丰富的接口，广泛应用于多个领域： - **工业自动化**：利用其强大的控制能力和高速通信接口，适用于制造过程控制、设备联网和数据采集。 - **医疗设备**：高精度的ADC和DAC，加上稳健的处理器性能，适用于医疗监测和治疗设备。 - **网络通信**：集成的Ethernet和USB接口，以及多种串行通信选项，适用于路由器、交换机和其他网络设备。 - **汽车电子**：CAN通道支持车辆内的网络通信，适用于汽车电子系统的开发。 LPC2368不仅是一款功能强大的微控制器，还具有高度灵活性和扩展性，适用于广泛的工业和消费电子领域。掌握其特性和应用，对于从事嵌入式系统设计和开发的专业人士来说，无疑是一笔宝贵的财富。

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1. General description

The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S

CPU with real-time emulation that combines the microcontroller with up to 512

kB of

embedded high-speed flash memory. A 128-bit wide memory interface and a unique

accelerator architecture enable 32-bit code execution at the maximum clock rate. For

critical performance in interrupt service routines and DSP algorithms, this increases

performance up to 30

% over Thumb mode. For critical code size applications, the

alternative 16-bit Thumb mode reduces code by more than 30

% with minimal

performance penalty.

The LPC2364/65/66/67/68 are ideal for multi-purpose serial communication applications.

They incorporate a 10/100 Ethernet Media Access Controller (MAC), USB full speed

device with 4

kB of endpoint RAM (LPC2364/66/68 only), four UARTs, two CAN channels

(LPC2364/66/68 only), an SPI interface, two Synchronous Serial Ports (SSP), three I

interfaces, and an I

S interface. This blend of serial communications interfaces combined

with an on-chip 4

MHz internal oscillator, SRAM of up to 32 kB, 16 kB SRAM for Ethernet,

kB SRAM for USB and general purpose use, together with 2 kB battery powered SRAM

make these devices very well suited for communication gateways and protocol

converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, one PWM unit, a

CAN control unit (LPC2364/66/68 only), and up to 70 fast GPIO lines with up to 12 edge

or level sensitive external interrupt pins make these microcontrollers particularly suitable

for industrial control and medical systems.

2. Features

 ARM7TDMI-S processor, running at up to 72 MHz

 Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. Flash program memory is on the ARM

local bus for high performance CPU access.

 8 kB/32 kB of SRAM on the ARM local bus for high performance CPU access.

 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

 8 kB SRAM for general purpose DMA use also accessible by the USB.

 Dual Advanced High-performance Bus (AHB) system that provides for simultaneous

Ethernet DMA, USB DMA, and program execution from on-chip flash with no

contention between those functions. A bus bridge allows the Ethernet DMA to access

the other AHB subsystem.

 Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

 General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP

serial interfaces, the I

S port, and the Secure Digital/MultiMediaCard (SD/MMC) card

port, as well as for memory-to-memory transfers.

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash

with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC

Rev. 06 — 1 February 2010 Product data sheet

Product data sheet Rev. 06 — 1 February 2010 2 of 59

NXP Semiconductors

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers

 Serial interfaces:

 Ethernet MAC with associated DMA controller. These functions reside on an

independent AHB.

 USB 2.0 full-speed device with on-chip PHY and associated DMA controller

(LPC2364/66/68 only).

 Four UARTs with fractional baud rate generation, one with modem control I/O, one

with IrDA support, all with FIFO.

 CAN controller with two channels (LPC2364/66/68 only).

 SPI controller.

 Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA

controller.

 Three I

C-bus interfaces (one with open-drain and two with standard port pins).

 I

S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

 Other peripherals:

 SD/MMC memory card interface (LPC2367/68 only).

 70 general purpose I/O pins with configurable pull-up/down resistors.

 10-bit ADC with input multiplexing among 6 pins.

 10-bit DAC.

 Four general purpose timers/counters with a total of 8 capture inputs and 10

compare outputs. Each timer block has an external count input.

 One PWM/timer block with support for three-phase motor control. The PWM has

two external count inputs.

 Real-Time Clock (RTC) with separate power pin, clock source can be the RTC

oscillator or the APB clock.

 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the

rest of the chip is powered off.

 WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

 Standard ARM test/debug interface for compatibility with existing tools.

 Emulation trace module supports real-time trace.

 Single 3.3 V power supply (3.0 V to 3.6 V).

 Four reduced power modes: idle, sleep, power-down, and deep power-down.

 Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0

and Port 2 can be used as edge sensitive interrupt sources.

 Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet

wake-up interrupt).

 Two independent power domains allow fine tuning of power consumption based on

needed features.

 Each peripheral has its own clock divider for further power saving.

 Brownout detect with separate thresholds for interrupt and forced reset.

 On-chip power-on reset.

 On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.

 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as

the system clock. When used as the CPU clock, does not allow CAN and USB to run.

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imthypal

2011-11-29

骗人呀，全都是2100系列的

wjguo_1

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