ddr_design

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ddr 设计资料 非常好的设计资料
MICRON DesignLine MAXIMUM ALLOWABLE INDUCTANCE separately from Lmax for V2.5. For simplicity of The fast switching current induces a voltage calculations, assume that only Idc flows from MVTT drop in the parasitic inductance of the capacitor and lac flows from V2. 5. In reality, MVTT contrib and the vias that attach it to the voltage planes utes to the Iac current flow during the edge transi- From the standard equation V=L(di/dt),Lmax can tion, but estimating or calculating that contribu- be calculated. There are two current paths that tion would likely not affect the results signifi ultimately flow through the driver. In the case of a cantl 1-to-0 transition, luc flows through Rs and rt. Iac Also note di for MVTT equals twice Idc. This is flows from the charged input gates through Rs and bccause Iac transitions from a positive value to a the driver into the ground plane. In the case of a negative value of the same magnitude. Iac transi- 0-to-1 transition the same current flows in the tions from O to its maximum value during dt other direction from v2.5 the tolerance of mvtt therefore di for V2. 5= Iac(scc Formula 3) is much tighter than V2.5, therefore, Lmax for the termination voltage mitt, should be calculated EQUIVALENT INDUCTANCE PER CAPACITOR Package inductance for a 0603 cap can vary from manufacturer to manufacturer and from one dielectric type to another. Designers should check component data sheets for the correct inductance here V= max allowable voltage drop value if available(see Formula 4) N(dn dt= 1000-90% switching time di current per net N-number of nets switching simultaneously- 109 NUMBER OF CAPACITORS NEEDED To calculate the number of capacitors needed, Note:. For di use 2 x ldc for MVTT and lac for V2.5 Tolerance specification for mItt is gom divide the equivalent inductance of each cap b Tolerance specification for V2.5 is 200mV the maximum allowable inductance, lmax (see s a For this example: Formula 5) MVTT Lmax=0.037nH The capacitor count for Mvtt may be reduced V2.5 Lmav=0.104nH depending on implementation. Some designs may allow Mitt to be implemented on a surface layer island, in which case one terminal of the cap can be attached directly to the plane without a Formula 3. Maximum Allowable Inductance Additionally, the effective length of the gr round via may be significantly reduced if the PCB stackup has the ground plane immediately below the If this is the case(assuming 004),Via= 29. 87pH, which gnificant For this example compared to the capacitor package inductance 0603 cap was used with a package inductance of 0. 87nH 0603 Leg Package Lvia= 2. 96nH Therefore, for surface plane decoupling, assume leq Package. Given this assumption, the 0603 capaci tor count for mitt would be 24. for internal Formula 4 Capacitor Equivalent Inductance planes, the 0603 capacitor count equals 80. Because the tolerance on MVtt is so tight, it is recom mended that a surface planc or somc other mcthod of lowering via inductance be used EXCEPTIONS AND VARIATIONS The equations presented here use a linear For this example: 0603 capacitor count is 80 for MVTT approximation of differential quantities such as di/ Capacitor count for V2. 5 is 28 dt. More in-depth calculations can be done to get more accurate predictions. Additionally, each net Formula 5. Number of Capacitors Needed was assumed to be equally loaded and of the same type In an unbuffered dDr channel, address DesignLine control, and clock signals will be more heavily loaded than data or strobes. These signals are also unidirectional from controller to RAM and they run at half the speed of data and strobes separate calcula tions can be done to more accurately predict the current flow for these nets The capacitor quantities in this example are very dependent on the device parameters used in the calculation. This analysis should be done for each new design as device parameters may be different and will significantly affect thc results. For instance, these calculations were based on using rs 10 ohms and Rt 56 ohms. Changing these values to 22 and 29, for example, will increase the amount of lc per net to 24.5mA. This reduces mvtt lmax to o286nh and increases the mvtt capacitor count to 30 in the case of the surface plane island and 103 for the internal plane Although difficult to predetermine, lower series resistance, Rs will also speed up signal edges, resulting in a larger di/dt quantity. This will increase the number of decoupling caps needed for V2.5 It is also difficult to predict what value should be used for dt. This is highly dependent on the strength of the driver being used and will vary greatly from one product family to another. Even in a fully Eric bokin loaded configuration, some devices have been measured to have edge Integrated Products Group, Senior Design Engineer ratcs of 2 V/ns, cffcctivcly switching in half the timc. These devices meet all of the minimum specs for DDR SDRAMs and might run in the same system with devices that only drive l V/ns. But the faster Eric is a senior design engineer with 4) devices switch the same amount of current over a lower dt time, Micron architectures labs. prior to hence they generate significantly more switching noise and, conse- joining Micron two years ago, he quently, may require additional decoupling to compensate for the worked at Hewlett-Packard for ten years driver strength designing controller boards and ASICs It is recommended that some experimentation be done to deter for Laser/et printers the most accurate data sheet information available to design a mlls o mine the right amount of decoupling needed. Use the equations ar prototype. Then, measure noise lcvcls on MVTT and v2. 5, and cdge rates of data and strobes to correlate noise with decoupling amounts New calculations based on these new measurements will give a more accurate estimate of the decoupling needs of the design

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