Revision History
5
December 2003 − Revised December 2005 SPRS231E
PAGE(S)
NO.
ADDITIONS/CHANGES/DELETIONS
163 Table 3−70, DSP DMA Controller Registers:
− updated address of DSP_DMA_CDFI1 (Channel 1 Destination Frame Index)
− updated address of DSP_DMA_CDEI1 (Channel 1 Destination Element Index)
− updated address of DSP_DMA_CDFI2 (Channel 2 Destination Frame Index)
− updated address of DSP_DMA_CDEI2 (Channel 2 Destination Element Index)
− updated address of DSP_DMA_CDFI3 (Channel 3 Destination Frame Index)
− updated address of DSP_DMA_CDEI3 (Channel 3 Destination Element Index)
− updated address of DSP_DMA_CDFI4 (Channel 4 Destination Frame Index)
− updated address of DSP_DMA_CDEI4 (Channel 4 Destination Element Index)
− updated address of DSP_DMA_CDFI5 (Channel 5 Destination Frame Index)
− updated address of DSP_DMA_CDEI5 (Channel 5 Destination Element Index)
167 Table 3−77, DSP Level 2.1 Interrupt Handler Registers:
− updated addresses of DSP_L21_SIR_IRQ_CODE through DSP_L21_ILR15 registers
− removed DSP_L21_ISR (Software Interrupt Set Register) from 0x00 4C0Ah
168 Table 3−78, DSP TIPB Bridge Configuration Register:
− 0x00 0000:
− changed REGISTER NAME from DSP_ID to DSP_CMR
− changed DESCRIPTION from “Identification Register” to “DSP Control Mode Register”
− removed all the registers from 0x00 0002 to 0x00 006E
168 Table 3−79, DSP EMIF Configuration Registers:
− 0x00 0800 (DSP_EMIF_CNTL): changed RESET VALUE from 002xh to 0000h
− 0x00 0801: changed from Reserved to DSP_EMIF_GRR (DSP EMIF Global Reset Register)
− removed all the registers from 0x00 0802 to 0x00 0814
170 Section 3.4, DSP External Memory (Managed by MMU):
− updated “When the DSP MMU is on, ...” paragraph
170 Figure 3−2, DSP MMU Off:
− DSP Memory: changed “0x05 0000” to “0x02 8000”
171 Figure 3−3, DSP MMU On:
− DSP Memory: changed “0x05 0000” to “0x02 8000”
176 Updated Section 3.6.6, Pulse-Width Light (PWL)
176 Updated Section 3.6.8, HDQ/1-Wire Interface
177 Section 3.6.10, MPUIO Interface:
− updated “The MPUIO feature allows communication ...” paragraph
180 Section 3.7.2, Multichannel Serial Interfaces (MCSI1 and 2):
− changed “Programmable interrupt occurrence time (TX and RX)” to “Programmable interrupt condition (TX and RX)”
181 Section 3.8.2, General-Purpose Timers:
− changed “Interrupts generated on overflow, compare, and capture” to “Interrupts generated on overflow and compare”
182 Section 3.8.3, Serial Port Interface (SPI):
− updated “The serial port interface is a bidirectional ...” paragraph
182 Updated Section 3.8.4, Universal Asynchronous Receiver/Transmitter (UART)
184 Updated Section 3.8.5, I
2
C Master/Slave Interface
185 Section 3.8.7, Multimedia Card/Secure Digital (MMC/SDIO2) Interface:
− changed “OMAP5912 also support control signals ...” bullet item to “The MMC2 provides auxiliary signals for external
level shifters ...”
