ug_ram_rom[1].pdf

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Embedded Memory (RAM: 1-PORT, RAM 2-PORT, ROM: 1-PORT, and ROM: 2-PORT User Guide
TOC-3 Simulating the design Document Revision history. ·。··B··. A-1 Document revision history ,A-1 Altera Corporation about rAm: 1-PORT, RAM: 2-PORT ROM: 1 PORt, and roM: 2-PORT IP Cores 2014.12.17 UG01068 X Subscribe Send feedback The quartus ii software automatically selects one of megafunction Ip cores to implement memory modes. The selection depends on the target device, memory modes, and features of the RaM and rom Table 1-1: IP Cores for Embedded Memory blocks This table lists the Ip cores for embedded memory blocks P Core Memory Mode RAM: 1-PORT Single-port RAM RAM: 2-PORT Dual-port ram ROM: 1-PORT Single-port ROM ROM: 2-PORT Dual-port ROM Embedded Memory Features The embedded memory blocks provide the following features Memory Modes Configuration Memory block types Write and Read Operations Triggering Port width Configuration Mixed-width port Configuration Maximum block depth confi ig uration Clocking Modes and Clock enable Address clock enable Byte enable Asynchronous Clear Read Enable Read-During- Write Power-Up Conditions and Memory Initialization Error Correction code 2014 Altera Corporation All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.s. Patent and Trademark office and in other countries. all other words and logos identified as trademarksorservicemarksarethepropertyoftheirrespectiveholdersasdescribedatwww.altera.com/common/legal.htmlAlterawarrantsperformance of its semiconductor products to current specifications in accordance with Altera's standard warranty but reserves the right to make changes to any 9001:2008 products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered product, or service described herein except as expressly agreed to in writing by altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services AUERA 101 Innovation Drive, San Jose, CA 95134 1-2 UG-01068 Supported Memory Operation Modes 2014.12.17 Supported Memory Operation Modes This table lists the supported memory operation mode and the related IP core for each operation mode Table 1-2: Supported Memory Operation Modes Memory Operation Mode Related IP Core Description Single-port RAM RAM: 1-PORT IP Single-port mode supports non-simultaneous read and write operations from a single address. Use the read enable port to control the RAM output ports ehavior during a write operation To show either the new data being written or the old data at that address, activate the read enable during a write operalion To retain the previous values that are held during the most recent active read enable, perform the write operation with the read enable port deasserted RAM: 2-PORT IP You can simultaneously perform one read and one write RAM Core operations to different locations where the write operation happens on port A and the read operation happens on port B True dual-port RAMRAM: 2-PORT IP You can perform any combination of two port operations ore two reads, two writes, or, one read and one write at two different clock frequencies Single-port ROM ROM: 1-PORT IP Only one address port is available for read operation C You can use the memory blocks as a ROM Initialize the ROM contents of the memory blocks using a mif or hex file The address lines of the rom are registered The outputs can be registered or unregistered The ROM read operation is identical to the read operation in the single-port RAM configuration Dual-port ROM ROM: 2-PORT IP The dual-port ROM has almost similar functional ports as ore single-port ROM. The difference is dual-port ROM has an additional address port for read op You can use the memory blocks as a ROm Initialize the rom contents of the memory blocks using if or hex file The address lines of the rom are registered The d outputs can be registered or unregis The Rom read operation is identical to the read operation in the single-port RAM configuration Altera Corporation About RAM: 1-PORT, RAM: 2-PORT ROM: 1-PoRT, and ROM: 2-PORT IP Cores Send feedback Customizing Embedded Memory IP Cores 2014.12.17 UG01068 X Subscribe Send feedback Installing and Licensing IP Cores The Altera IP Library provides many useful IP core functions for production use without purchasing an additional license. You can evaluate any Altera IP core in simulation and compilation in the Quartus II software using the Open Core evaluation feature. Some Altera IP cores, such as Mega core functions require that you purchase a separate license for production use. You can use the Open Core plus feature to evaluate Ip that requires purchase of an additional license until you are satisfied with the functionality and performance. After you purchase a license, visit the Self Service Licensing Center to obtain a license number for any Altera product Figure 2-1: IP Core Installation Path acas quartus-Contains the Quartus ll software ip-Contains the altera IP Library and third-party IP cores [ altera-Contains the Altera IP Library source code H</P core name>-Contains the lP core source files Note: The default IP installation directory on Windows is <drive> alteral< version number; on Linux it is <home directory>/altera/<version number> Related information Altera Licensing Site Altera Software Installation and Licensing Manual 2014 Altera Corporation All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.s. Patent and Trademark office and in other countries. all other words and logos identified as trademarksorservicemarksarethepropertyoftheirrespectiveholdersasdescribedatwww.altera.com/common/legal.htmlAlterawarrantsperformance of its semiconductor products to current specifications in accordance with Altera's standard warranty but reserves the right to make changes to any 9001:2008 products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered product, or service described herein except as expressly agreed to in writing by altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services AUERA 101 Innovation Drive, San Jose, CA 95134 UG-01068 2-2 IP Catalog and Parameter Editor 2014.12.17 IP Catalog and Parameter editor The Qsys IP Catalog (tools >IP Catalog) and parameter editor help you easily customize and integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate files representing your custom IP variation The Virtual Processing Image Suite is available only through the Qsys IP Catalog(View >IP Catalog) Double-click any IP core name to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify your ip variation name, optional ports, architec ture features, and output file generation options. The parameter editor generates a top-level qsys file representing the IP core in your project. Alternatively, you can define an IP variation without an open Quartus II project. When no project is open, select the Device Family directly in IP Catalog to filter IP cores by de Use the following features to help you quickly locate and select an IP core Filter IP Catalog to Show iP for active device family or Show IP for all device familie Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access partner IP information on the Altera website. Right-click an IP core name in IP Catalog to display details about supported devices, installation location, and links to documentation Note: The IP Catalog and parameter editor replace the Mega Wizard Plug-In Manager in the Quartus II software. The Quartus II software may generate messages that refer to the Mega Wizard Plug-In Manager. Substitute IP Catalog and parameter editor"for "Mega Wizard Plug-In Manager"in these messages pgrading VIP Designs in 14.0 In Quartus, if you open a design from a 13. 1 or previous version that contains vip components in a Qsys system, Quartus will show a warning message with the title Upgrade IP Components". This message is just letting you know that VIP components within your Qsys system need to be updated to their latest versions, and to do this the Qsys system must be regenerated before the design can be compiled within Quartus. The recommended way of doing this with a VIP system is to close the warning message and open the design in Qsys so that it is easier to spot any errors or potential errors that have arisen because of the design being upgraded Related Information Creating a System With Qsys For more information on how to simulate Qsys designs Using the Parameter Editor The parameter editor helps you lo configure IP core ports, parameters, and oulput file generation options Use preset settings in the parameter editor (where provided)to instantly apply preset parameter values for specific applications View port and parameter descriptions, and links to documentation Generate testbench systems or example designs (where provided) Altera Corporation Customizing Embedded Memory IP Cores □ Send feedbacl UG01068 2014.12.17 Specifying IP Core Parameters and Options 2-3 igure 2-2: IP Parameter Editors IP Pararmeter Editor.unnamed qsys(use/brus 上 tan system cene ate lew 100s n Patameters 3e and parameter unsaved aitclkdrl 0 details ALTCLKCTRL ALTCLKCTRL alticor rsion about thls Cor Author Altera c k butlers tha dive the Global Chek Networ the Regional Cork Tiu ate dacia eu Extera cluCk pah. escriotion no description How do you want to use the ATCKCTFL: For al bal click- Legacy parameter PLLs and Resets Altclkctrl editors arable Crtele end purr lo enable ut hisel- the tluck newu k driven Ly ias bule? ENsure cltch-free switchover mplementation Preses for atclkctrL o Iop-level Name LPM MULT [ CIck New, To create a pr Presets for ALTCLKCERL 14.0 Devile FamIly xu (X Hi te Info Your t will ba s HowMOeghwoMthe Stay inotbe D o Brus, o Warp Specify your /P variation name Apply preset parameters fo roor:eu C wi:dBxk Net=[Een] and target device specific applications Specifying IP Core Parameters and options The parameter editor GUI allows you to quickly configure your custom IP variation. You specify IP core options and parameters in the Quartus II software 1. In the IP Catalog (Tools>IP Catalog), locate and double-click the name of the ip core to customize The parameter editor appears 2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your ip>qsys. Click OK 3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters. Optionally select preset parameter values if provided for your ip core. Presets specify initial parameter values for specific applications Specify parameters defining the Ip core functionality, port configurations, and device-specific eatures Specify options for processing the IP core files in other EDa tools 4. Click Generate HDL, the Generation dialog box appears 5. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications 6. To generate a simulation testbench click generate Generate Testbench System Customizing Embedded Memory IP Cores Altera Corporation Send Feedback UG-01068 2-4 Migrating IP Cores to a Different Device 2014.12.17 7. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate>HDL Example 8. Click Finish. The parameter editor adds the top-level qsys file to the current project automatically. If you are prompted to manually add the qsys file to the project, click Project Add/Remove Files in Project to add the file 9. After generating and instantiating your IP variation, make appropriate pin assignments to connect Figure 2-3: IP Parameter Editor IP Pa ter Editor amed. gsys (/users/jbro ssar/unnamed qss) ew∥Pp0 Fille Edi systen generate view Tcols ep 了口|旧 Details Sym8 and parameter details ALTCLKCTRL ALTCLKctrl tclkctrl altclkctrl AltcIkctrl Version Altera Corporation Altdkctrl reore oct buffers that drve the Gloo al Clock Netwok the Regional Clock Netwo and the dedicated External Clock path. Descri ption no description How co you want to use the ALTCLKCTRL: For globa cock Gro Basic Functio ns /Clo cks DCreate'ana' port to enable or disable the clock network driven by: his buffer? Altclkctrl Ensure glitch-free switchover implemetation Your IF setIngs wlll oe saved la a, csys nle Preses for aitclkctr-0 Device settings No presets for ALTCLKCTRL 14.0 Measues Devce Unknow Tvpa @ Info: Your r will be saved n unnam o unsc Delete N 0 Ermor, 0 Mannings Generate HDL. Finish Specify your /P variation name Apply preset parameters for and target device pecific applications Migrating IP Cores to a Different Device IP migration allows you to target the latest device families with iP originally generated for a different device. Some Altera IP cores require individual migration to upgrade. The Upgrade IP Components dialog box prompts you to double-click IP cores that require individual migration 1. To display IP cores requiring migration, click Project Upgrade IP Components. The Description field prompts you to double-click IP cores that require individual migration 2. Double-click the IP core name, and then click ok after reading the information panel The parameter editor appears showing the original Ip core parameters 3. In the parameter editor, click Generate, and then click OK if prompted to overwrite IP files Altera Corporation Customizing Embedded Memory IP Cores □ Send feedbacl UG01068 2014.12.17 Migrating IP Cores to a Different Device 2-5 The new parameter editor appears when the generation is complete 4. Click Generate HDL, and then confirm the Synthesis and Simulation file options. Verilog is the parameter editor default HDl for synthesis files. If your original IP core was generated for VHDL, select VhDl to retain the original output HDl format 5. To regenerate the new IP variation for the new target device, click Generate. When generation is complete click close 6. Click Finish to complete migration of the IP core. Click OK if you are prompted to overwrite IP core files. The Device Family column displays the migrated device support. The migration process replaces <my_ip> qip with the <my_ip> qsys top-level IP file in your project Note: If migration does not replace <my_ip> qip with <my_ip> qsys, click Project> Add/Remove Files in Project to replace the file in your project 7. Review the latest parameters in the parameter editor or generated HDL for correctness. IP migration may change ports, parameters, or functionality of the IP core. During migration, the Ip core's hDL generates into a library that is different from the original output location of the ip core. Update any assignments that reference outdated locations. If your upgraded ip core is represented by a symbol in a supporting Block Design File schematic, replace the symbol with the newly generated <my_ip>. bsf after migration Note: The migration process may change the IP variation interface, parameters, and functionality This may require you to change your design or to re-parameterize your variant after the Upgrade IP Components dialog box indicates that migration is complete. The Description field identifies ip cores that require design or parameter changes Related information Altera ip release notes Customizing Embedded Memory IP Cores Altera Corporation Send Feedback

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